VMEbus
The VMEbus ( V ersa M odule E urocard- bus ), and VME bus or VME bus system called, is a multi-user bus system for the control technology , which was originally for the 1981 Motorola processor family 68000 was developed. The VMEbus currently supports almost all processors, e.g. B. Intel x86 , HP PA-RISC , Motorola 88000 and PowerPC . It was standardized by the IEC as ANSI / IEEE 1014–1987.
The original variant had a 16-bit data bus and 24-bit address bus , for which various extensions were later developed. With the current VME64 version, 64-bit bus width is available. The VMEbus is used, among other things, in the aerospace industry; the ISS computer is based e.g. B. on the VMEbus, albeit in a different design.
The bus is a backplane bus ( backplane bus without its own electronic components) for 19 ″ slide-in housing.
The VMEbus was designed by a consortium led by Motorola and Philips . Companies that VMEbus components develop and distribute in the VITA ( V MEBUS I nternational T rade A ssociation) organized, users have also joined forces in organizations.
In competition with the VMEbus, Intel launched a comparable bus based on 80x86 processors under the name Multibus II , but it was not nearly as successful as the VMEbus and its further developments.
connections
Plug connections
The boards and assemblies (plug-in units) are plugged into the VMEbus with connectors according to DIN 41612 and IEC 603-2. These have 3 rows with 32 contacts each, i.e. 96 contacts per connector. Depending on the expansion stage, the connections P1 , P2 and P3 (latest expansion - only in the VXI bus) are assigned.
General information about the connections
The bus and interrupt control, the data bus lines D00 to D15 and address bus lines A01 to A23 are located on the connection P1 .
The connection P2 contains the data bus lines D16 to D31 and the address bus lines A24 to A31 in the middle row (row B) . Rows A and C are not defined in the VMEbus, they are unoccupied, defined by the user or used by a subbus. The VMX or VSB are defined as subbuses .
The connection P3 contains the extensions of the VXI bus.
Terminal assignment on P1
| ## | Row A | Row B | Row C |
|---|---|---|---|
| 01 | D00 | / BBSY | D08 |
| 02 | D01 | / BCLR | D09 |
| 03 | D02 | / ACFAIL | D10 |
| 04 | D03 | / BG0IN | D11 |
| 05 | D04 | / BG0OUT | D12 |
| 06 | D05 | / BG1IN | D13 |
| 07 | D06 | / BG1OUT | D14 |
| 08 | D07 | / BG2IN | D15 |
| 09 | GND | / BG2OUT | GND |
| 10 | SYSCLK | / BG3IN | / SYSFAIL |
| 11 | GND | / BG3OUT | / BERR |
| 12 | DS1 | / BR0 | / SYSRESET |
| 13 | DS0 | / BR1 | / LWORD |
| 14th | / WRITE | / BR2 | AM5 |
| 15th | GND | / BR3 | A23 |
| 16 | / DTACK | AM0 | A22 |
| 17th | GND | AM1 | A21 |
| 18th | / AS | ON 2 | A20 |
| 19th | GND | AT 3 | A19 |
| 20th | / IACK | GND | A18 |
| 21st | / IACKIN | SERCLK | A17 |
| 22nd | / IACKOUT | SERDAT | A16 |
| 23 | AT 4 | GND | A15 |
| 24 | A07 | / IRQ7 | A14 |
| 25th | A06 | / IRQ6 | A13 |
| 26th | A05 | / IRQ5 | A12 |
| 27 | A04 | / IRQ4 | A11 |
| 28 | A03 | / IRQ3 | A10 |
| 29 | A02 | / IRQ2 | A09 |
| 30th | A01 | / IRQ1 | A08 |
| 31 | −12V | + 5V (batt) | + 12V |
| 32 | + 5V | + 5V | + 5V |
Legend
| command | designation |
|---|---|
| D00 - D15 | Data bus lines |
| A01 - A23 | Address bus lines |
| AM0 - AM5 | Address modifier |
| / BR0 - BR3 | Bus requirements |
| / BG0IN - / BG3IN | Bus releases (input) |
| / BG0OUT - / BG3OUT | Bus releases (output) |
| / IRQ1 - / IRQ7 | Interrupt requests |
| / IACK | Interrupt acknowledgment |
| / IACKIN | Interrupt confirmation (input) |
| / IACKOUT | Interrupt acknowledgment (output) |
| / ACFAIL | Disturbance in the network (voltage) |
| / BERR | Bus error |
| / SYSFAIL | System error |
| / SYSRESET | System reset |
| SYSCLK | System clock 16 MHz (not required for bus control) |
| / LWORD | Longword transfer |
| / BBSY | Bus occupied |
| / BCLR | Request for bus release |
| / WRITE | Write cycle |
| / DS0 - / DS1 | Data bus selection |
| SERCLK | Serial bus (clock) |
| / SERDAT | Serial bus (data) |
| GND | Dimensions |
| + 5V | Supply voltage 5 volts |
| + 5V (batt) | Supply voltage 5 volts from battery |
| + 12V | Supply voltage 12 volts |
| −12V | Supply voltage −12 volts |
Bus control lines
The bus control lines are used for allocation and release in the data bus. This includes the lines / BR0 to / BR3 , they are the bus requests (bus request), they are L -active. Each slot can start a bus request, in which the corresponding line of L is set.
The lines / BG0OUT to / BG3OUT are the bus grants as outputs, / BG0IN to / BG3IN are the inputs. These lines are wired in such a way that an output / BGxOUT is forwarded to the next module at the input / BGxIN . This daisy-chain circuit enables the release to be passed on to the next module. Unused slots must be bridged with jumpers , otherwise the transfer chain is interrupted. This technology ensures that the four bus requests can be used by any number of slots, but this has the side effect that slots further to the left have a higher probability of being allocated.
If a module occupies the bus, it indicates it with an L on the line / BBSY (Bus Busy). The counterpart to this is the line / BCLR , which is controlled by the arbiter and requests the module with an L to release the bus again and to end the transmission.
The line / DTACK (Data Acknowledge) indicates with L that a data bus transfer was successful. An L on the line / BERR indicates that the transmission has failed .
Lines DS0 and DS1 together with LWORD and (within limits) AD01 define which data groups of an 8-, 16- or 32-bit word are on which data lines. This somewhat confusing method made it possible to transfer data groups on different bus widths and in different address spaces.
In addition, the lines AM0 to AM6 are used to assign address spaces and types of transmission. A distinction is made between 16-, 24- and 32-bit address spaces, between block and byte / word transfer, between data and program transfer, with or without privilege.
Interrupt lines
The interrupt requests are made via the lines IRQ1 to IRQ7 . Unlike the arbitration, the interrupt control can also be handled by others than the first module. For this purpose, an IACK (Interrupt Acknowledge) line is implemented as an output, which becomes an IACKIN before the first slot , which is then always passed on via IACKIN and IACKOUT , as with bus assignment . In the drawing, the connections are red, which are bridged by a jumper if there is no slot. Only 3 of the 20 possible slots are shown, the series would always continue. There is only one such IACK channel; the number of the interrupt that is currently being handled is transmitted in address bits A1 to A3 .
Working method
Interrupt and bus control require an arbiter to regulate the interrupt and bus requirements. The arbiter is usually located in the first slot.
Interrupts
The VMEbus has seven IRQ lines that have different priorities. However, each interrupt can be used by any number of boards, since the interrupt vector is not determined by the IRQ line, the requesting board specifies the interrupt vector itself. In detail, an interrupt request is made in such a way that the requesting unit sets the interrupt request (one from IRQ1 to IRQ7 ) to L in the first step . The unit that is responsible for handling interrupts gets access to the bus with the highest priority, if it does not already have it. The unit then sends the number of the interrupt request to be processed on A01 to A03 and an L on the / IACK line . The signal is then forwarded via / IACKIN and / IACKOUT from left to right from one slot to the next; the first unit that made this request sends back the actual interrupt vector (00h to FFh) on the data bus on D00 to D07 . This interrupt vector is then processed.
The great advantage of this procedure, which at first seems unnecessarily complicated, is that many units can share the IRQ lines without provoking interrupt conflicts, as is the case in the ISA , VLB and PCI bus happens again and again. It should be noted that the VMEbus was historically developed and launched on the market before the bus systems just mentioned.
Bus control
The VMEbus is a multi-master bus, which means that several bus masters can occupy the bus. Here, too, priorities are used, four BRQ lines are available that are assigned strictly priority or work in the round robin process with rotating priorities. A fairness procedure is operated with the latter, units that wait longer are preferred. However, the purely priority procedure is more common.
The arbiter for bus allocation is usually located in the first slot because there is no common BGx line . An arbiter who sits elsewhere can only control the units that are installed to the right of him. The slots to the left would then be lost.
VMSbus and VMXbus
The VMXBus ( VM E x tended bus ) specifies the connection of a memory. The data path to this is 32 bits wide, an address comprises 24 bits, which are multiplexed as two 12-bit words. A ribbon cable establishes the connection between two cards.
About the VMSbus ( VM E S erial bus ) messages / s transmitted with 200 to 400 MB.
Applications
Web links
- VITA (English)
- Virtual company museum (dedicated to VMEbus machines, among others)
Individual evidence
- ↑ Thomas Flik: Microprocessor technology . 2001, ISBN 3-540-42042-8