Elbrus 2000

from Wikipedia, the free encyclopedia

The Elbrus 2000 (Эльбрус 2000, E2K ) is a Russian microprocessor based on a 512-bit wide VLIW - EPIC - architecture . It was developed by МЦСТ ( MZST , Moscow Center for SPARC Technology ).

The Elbrus 2000 was planned as a microprocessor continuation of the Elbrus 3 processor architecture. It uses a binary compilation technology to achieve compatibility with the Intel x86 architecture. The design was implemented on standard cells at the Taiwanese contract manufacturer TSMC and manufactured from June 2008.

As of September 2009, production is in the new plant of Angstrem in Zelenograd planned. The equipment used by AMD from Fab 30 is suitable for a 130 nanometer process with 200 millimeter wafers .

Technical specifications

The Elbrus 2000 builds on the ELBRUS architecture ( e xp L ICIT B asic R esources U tilization S cheduling - similar EPIC ) whose special feature is the parallelization of resources for a time-parallel execution of explicit instructions parts in one is VLIW instruction. As the architecture successor to Elbrus 3, the Elbrus 2000 is rated as a microprocessor which - together with the appropriate compilers - realizes the “deepest parallelization known today” .

Its peak performance is 23.7 GIPS .

Data of the Elbrus 3M
Manufacturing process CMOS 0.13 µm
Work cycle 300 MHz
Top performance
  • 64 bit: 6.67 GIPS / 2.4 G FLOPS
  • 32 bit: 9.5 GIPS / 4.8 GFLOPS
  • 8/16 bit: 22.6 GIPS / 12.2 GFLOPS
Data format
  • whole numbers: 32, 64
  • Real numbers: 32, 64, 80
Cache memory
  • Cache-1 for instructions: 64 Kbytes
  • Cache-1 for data: 64 KByte
  • Cache-2: 256 KByte
Cache page table 512 inputs
Data rate of the channel to the cache
  • Channels to the cache: 9.6 GB / s
  • Channels to main memory: 4.8 GByte / s
Chip area 189 mm²
Gates 75.8 million
Metallization levels 8th
Housing type / connections HFCBGA / 900
Case size 31 × 31 × 2.4 mm
Supply voltages 1.05 / 3.3V
Power dissipation 6 W

history

MZST emerged after 1990 as an offshoot of the leading Soviet computer science institute SA Lebedev Institute for Precision Mechanics and Computing Technology of the Russian Academy of Sciences (IPMuRT; ИТМ и ВТ) and the Elbrus Group . The IPMuRT had developed about 30 years supercomputers, including about 15 years, the number Elbrus 1, 2 and Elbrus Elbrus Elbrus 3. Already one was characterized by a superscalar from -Parallel architecture, whereby the technical backwardness of components in the Soviet Union could be partially compensated. The Elbrus 3 computer, which was built from obsolete components until around 1990, could e.g. Thanks to its architecture, for example, it has twice the computing power than the most modern American supercomputer Cray Y-MP at the time . Boris Babajan was the chief designer of the Elbrus 3 .

On February 25, 1999, Babajan announced at the international Microprocessor Forum that his team had developed the Elbrus 2000, which clearly surpassed the upcoming Merced ( Intel Itanium ) in all respects.

The project became known in the West after Keith Diefendorff's article The Russians Are Coming in the Microprocessor Report 2/1999. Dave Ditzel , founder of the Transmeta company , was also positive about the project.

In 2005 it was announced that the Elbrus 3M chip Эльбрус-3м Кристалл for the Elbrus 3M computer was implemented and is being tested. In 2014 the media reported that a new generation, the "Baikal" CPU, is about to go into series production.

Data of the Elbrus 3M
power 1–2 billion operations / s. (Depending on the task)
Top performance 23.7 Giga-OPS / 2.4 GFLOPS (64 bit)
Project norm 0.13 µm
Gates 50 million

The E3M chip is a downgraded model that does not have a level 3 cache . Its logic was developed by MZST and other partners on the basis of a library of standard cells from the Taiwanese contract manufacturer TSMC. Its clock rate is 300 MHz.

In 2007, information was provided about the completion of the state tests of the Elbrus 3M computer complex based on test samples from the microprocessor of the same name. The computer was presented to the press for the first time in July 2008. In front of the public, the 300 MHz computer in Intel / IA-32 compatibility mode outperformed the 500 MHz Intel Pentium III in SPEC tests. It was thus proven that the binary compatibility with the IA-32 also works, i. H. the binary compiler, the mini operating system and the new architecture that were designed to be compatible with IA-32 work. That the Elbrus 3M works with the Elbrus code, which is widespread in Russia, was already clear after the state tests, where it had shown performance that was comparable to the 2 GHz version of the Intel Pentium 4 . The difference in speed is explained by the fact that precompilation optimizes the binary code of programs that were written for other architectures.

The developers have promised to deliver several hundred Elbrus 3M computer complexes for air defense and missile defense tasks in 2008. In addition, multi-core variants and the transition from 130 nm to faster technologies are planned.

successor

  • Elbrus-2S + manufactured by TSMC Taiwan in 2011
  • Elbrus-2SM, pre-series production 2014 by Mikron Russia
  • Elbrus-3M, test phase from 2005
  • Elbrus-4S, expected series production 2014
  • Elbrus-8S "Baikal" with 1 GHz, announced for 2014/2015
  • Elbrus-16C, announced for 2018
  • Elbrus-32C with 32 cores and 2 GHz, announced for 2020

Remarks

The fate of the E2K was influenced by the fact that Intel took over the Babajans company and its team in 2004. That affected around 500 engineers and researchers.

The patents for the processor are owned by International Elbrus Services on the Cayman Islands .

Web links