Status register

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The status register (also state register , English condition code register (CCR) , or program status word , English program status word (PSW) ) is a special register in the arithmetic unit of a microprocessor . Since these bits are also known as flags , the status register is also called a flag register. It contains a series of flags that are set by the arithmetic-logic unit (ALU) depending on the last calculation operation carried out (e.g. overflow , negative result ). Some flags can also be changed by direct instructions . Some processors - e.g. B. the 6502 - set most of the status flags during pure loading operations.


Conditional (jump) instructions depend exclusively on these flags and some arithmetic operations of the ALU are influenced by the state of the flags.

The content of the status register can be placed on the stack in order to save it. This happens automatically when an interrupt is called so that the program can continue to work undisturbed after the interrupt has ended.

The type and scope of the status register depends on the CPU architecture. However, a number of flags appear in most microprocessors today. These flags include:

General flags of a status register

Carry flag

If this flag is set, a carry occurred in the last arithmetic operation if one assumes unsigned operands . If the last command executed was a shift operation, the carry flag shows the value of the shifted bit.

Zero flag

If the zero flag is set, the last calculation result was zero.

In the case of a comparison command , two operands are internally subtracted without changing them. Then the zero flag indicates whether these two operands are equal.

Sign flag (negative flag)

Today's microprocessors use two's complement to represent signed numbers . You can recognize negative numbers by the set most significant bit. The sign flag is set according to this bit.

Overflow flag

If the overflow flag is set, an overflow occurred during the last arithmetic operation if one assumes signed operands . When comparing (internal subtraction) of signed values, you need conditional jump commands that depend not only on the overflow flag but also on the sign flag.

Parity flag

If the number of bits set for the last calculation result is even ( binary representation ), the parity flag is set. If the number is odd, it is deleted. With x86 processors , the parity flag is only formed using the least significant byte .

Interrupt Enable Flag (s)

This flag is not a status flag, but a control flag. If it is deleted, interrupts from the processor are suspended. You clear this flag at the beginning of interrupt routines (some processors do this automatically) so that they can run through to the end without being disturbed. After setting the interrupt enable flag, the processor first executes an instruction before it allows interrupts again. In an interrupt routine after setting this flag, you can still execute the RETURN command.

There are interrupts that remain unaffected by the interrupt enable flag. These are called non-maskable interrupts (NMI).

Some CPUs have several of these bits in order to be able to block or allow interrupts with different priorities.

Adjust flag

If a microprocessor has no special arithmetic instructions for binary coded decimal digits (BCD), this flag is often present. It is set in "normal" binary arithmetic operations when a carry occurs between the nibbles ; z. E.g. when adding 9 and 7 = 16: 1001 2 + 0111 2 = 1 0000 2 . This flag then indicates whether the result needs to be corrected. 1001 2 + 0111 2 = 0001 2 * (10 1 ) + 0110 2 * (10 0 ).

Other microprocessors have a BCD (status) flag with which you can set in advance whether the processor has to calculate with "normal" binary numbers or with dual-coded decimal digits.

BCD flag

This flag is not a status flag, but a control flag. If it is set, the processor arithmetic - the ALU - works in BCD mode instead of purely binary arithmetic. This is primarily intended to carry out financial calculations directly in the decimal system and to avoid inaccuracies when converting binary fixed or floating point numbers .

CPU architectures without arithmetic flags

Some RISC architectures do not have the usual status registers with corresponding flags. These include MIPS (as well as the MIPS-based Altera Nios ), DEC Alpha and AMD 29000 . With some CPU instructions, the corresponding status flags, such as the carry, are stored as bits in a universal register (such as r8), in other cases, such as when an arithmetic overflow is detected, longer substitute constructs are used multiple CPU commands.

See also