VIA Cyrix III
| VIA Cyrix III | |
|---|---|
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| Production: | 2000 to 2001 |
| Producer: | TSMC |
| Processor clock: | 350 MHz to 733 MHz |
| FSB cycle: | 100 MHz to 133 MHz |
| L2 cache size: | 0 KiB to 256 KiB |
| Instruction set : | x86 |
| Microarchitecture : | CISC |
| Base: | Base 370 |
Names of the processor cores:
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The VIA Cyrix III is an x86 processor for Socket 370 from VIA Technologies .
Originally, a real Cyrix processor was supposed to appear under the name VIA Cyrix III in early 2000 . This CPU had been in development for so long that it was given three different code names: Originally, development began under the name “Cayenne” when Cyrix was still independent. After the merger with National Semiconductor, the code name was changed to "Gobi". But the CPU could not be completed in the two years that it was part of NS. Only after the takeover by VIA was the CPU ready under the code name "Joshua".
Due to the long development time, one could actually expect a mature product, but the VIA Cyrix III was only a very interesting CPU for the Socket 370 on paper . Originally planned for the performance segment, it had to be rescheduled as a competitor for Intel's low-cost CPU Celeron because of the long delay . With a revised FPU , 256 KiB L2 cache and 133 MHz FSB, the Celeron should actually be an easy opponent, and the Joshua should have been clearly superior.
However, the Joshua disappointed in the first preliminary tests: instabilities, high heat generation and very low clock rates combined with completely utopian P-ratings (because they were set much too high) led VIA to completely abandon the Joshua design and instead use the Samuel developed by Centaur Technology as "VIA Cyrix III" sold.
This Samuel processor was brought onto the market in mid-2000 and was basically a WinChip 3 ported to Socket 370 with higher clock rates and better manufacturing technology. Because of the missing L2 cache (in the WinChip series, the L2 cache was on the mainboard, as was usual with Socket 7 , which was not available with Socket 370), the CPU was hardly competitive and is probably more than the first attempt at VIA the CPU market to see.
The successor Samuel 2 was then sold under the name VIA C3 .
Model data
Joshua
- Cyrix design
- Code name: initially "Cayenne", after takeover by National Semiconductor "Gobi", after takeover by VIA Technologies "Joshua"
- L1 cache: 64 KiB (unified)
- L2 cache: 256 KiB with processor clock
- MMX , 3DNow!
- Socket 370 , GTL + with 100 to 133 MHz front side bus
- Operating voltage (VCore): 2.2V
- Release DATE: February 2000
- Manufacturing technology: 0.18 µm at TSMC
- The size: unknown with 22.0 million transistors
- Clock rates: 350 MHz to 450 MHz
- PR433: 350 MHz (100 MHz FSB)
- PR466: 366 MHz (122 MHz FSB)
- PR500: 400 MHz (133 MHz FSB)
- PR533: 433 MHz (124 MHz FSB)
- PR533: 450 MHz (100 MHz FSB)
Samuel
- Centaur design
- Code name: C5A
- L1 cache: 64 + 64 KiB (data + instructions)
- L2 cache: nonexistent
- MMX , 3DNow! , LongHaul!
- Socket 370 , GTL + with 100 and 133 MHz front side bus
- Operating voltage (VCore): 1.90 V or 2.00 V.
- Power consumption ( TDP ): approx. 7 W to 10 W.
- Release DATE: June 2000
- Manufacturing technology: 0.18 µm at TSMC
- The size: 75 mm² with 11.3 million transistors
- Clock rates: 500, 550, 600, 650, 667, 700 and 733 MHz