Power architecture

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The power architecture (a backronym for P erformance o ptimized w ith e nhanced R ISC ) is a family of processors from the OpenPower Foundation. It was originally developed by IBM as the successor to the mainframe and midrange processors in bipolar and CMOS design.

With this processor architecture, IBM switched from 31 or 32-bit processors to 64-bit addressing. These processors were and are used in the IBM server series AS / 400 , RS / 6000 , later iSeries , pSeries and Z Systems . iSeries and pSeries were standardized in hardware by the POWER processors.

Z Systems have a CISC instruction set that is simulated on power processors using microcode from the power instruction set (actually a RISC, Reduced Instruction Set Computer ). This procedure is not uncommon among CPU manufacturers; x86 CISC processors also internally process RISC-like microcode. The hardware basis for the processors in the Z Systems and IBM Power processors is thus identical.

The branch of PowerPC processors for workstations has also been modified from the POWER platform. From generation POWER8 onwards, so-called Linux-based OpenPOWER server systems are also built that contain those processors.

In 2019 the instruction set architecture , English Instruction Set Architecture (ISA), was disclosed. It describes in detail the complete RISC architecture of the Power ISA so that companies can develop power processors without having to purchase licenses. Since February 2020, processors of the power architecture have generally been free of license costs, even for the production and sale of processors. This step is seen as a reaction to the license-free RISC-V architecture.

The Power Architecture Platform Reference , or PAPR for short, defines an open hardware platform for the Power and PowerPC architecture.

POWER

The single-chip processor PowerPC 601 , which emerged from the merger of Apple, IBM and Motorola (AIM alliance) , was initially modified from the original Power family . The power architecture quickly found use in the areas of workstation computers (Apple), in embedded systems and in space travel.

POWER2

The POWER2 SC , the first power processor from a single chip, was derived from the 1993 eight-chip processor POWER2 in 1996 and was sold until 1999.

POWER3

1998, published POWER3 and POWER3-II with a 64-bit CMOS6S2 technology, and 225 mm² (POWER3) or 170 mm (POWER3-II) The face.

POWER4

The IBM p690, called Regatta, implemented two CPU cores on one chip for the first time (initially POWER4 , 180 nm, 1.1–1.3 GHz from 2001 ), a shared L2 cache and a very fast switch interface. But the connection interfaces of these chips were also new. Four of these processor cores were connected on a common multi-chip module (MCM); IBM thus achieved the extremely high packing density of eight CPUs on an area of ​​90 cm². With 32 POWER4 + CPUs (from 2002: 130 nm, 1.2–1.9 GHz, 267 mm², 185 million transistors), the regatta achieved a peak performance of over 1 million points in the database benchmark tpm-C in March 2004 .

The PowerPC 970 developed by IBM emerged from the POWER4, which Apple called the G5 . It is considered the successor to the PowerPC G4 , which came from Motorola.

Power5

Power5 four-core MCM (2005)
Power5 + dual core module 1.9 GHz (2006)

Power5 130 nm 1.5; 1.65; 1.9 GHz dual-core processor, 389 mm², 276 million transistors, with simultaneous multithreading (SMT) and integrated memory controller . Cache: 64k2w-lru (instructions) and 32k4w-lru (data). L2 cache 1.92m10w-lru. in partitionable pSeries and iSeries SMP servers from 1 to 64 CPUs, 1 GB – 2 TB main memory and 5 - 240 PCI-X slots. A multi-chip module with four CPU chips (i.e. eight cores) and four 36 MB L3 cache chips consists of 89 metal layers with a total of 5370 I / O pins, of which 2313 are signal pins and 3057 are required for the power supply .

Power5 from 2004 is the further development of POWER4 . In addition to the POWER4 architecture, the L3 directory and the memory controller are located on the chip, plus a higher clock rate. Power5 is up to three times more powerful than POWER4 . IBM claimed that this provided the best scalability (linear up to 64 paths) of all servers on the market at the time. As another unique functionality, the Power5 architecture with Advanced Power Virtualization (APV) offers, among other things, the option of dividing the physical CPUs into virtual CPUs, which are then dynamically and automatically distributed between the various logical partitions ( LPARs ) during operation. APV has been sold under the name PowerVM since December 21, 2008 .

On October 4, 2005, IBM announced the Power5 + 90 nm dual-core processor with 1.5 or 1.9 GHz. From mid-2006 there were single and dual-core Power5 + processors with up to 2.3 GHz.

Power6

The Power6 processor was manufactured from 2007 in the 65-nm process and has a The mm² face of the 341st There are over 790 million transistors in this area. Most of the area is occupied by the 8 MiB L2 cache, of which half, i.e. 4 MiB, is allocated to each core. The size of the L1 cache is 128 KiB, divided into 64 KiB data and 64 KiB instruction caches. The external L3 cache with a size of 32 MiB can be addressed with a bandwidth of 80 GiB / s. The Power6 processors are 4.2; 4.7 and 5.0 GHz clock frequency available.

IBM sees this processor in the area of ​​company databases (e.g. IBM System p and IBM System i ) as well as high-performance computers such as those required in aircraft construction and in accident simulations in automobile construction.

Power7

The Power7 came onto the market in 2010 and consists of up to eight cores, each of which can execute up to four threads in parallel. The CPU is manufactured in 45 nm and the maximum clock frequency is 4.1 GHz.

The Power7 + CPU, which is manufactured in 32 nm and now reaches a maximum clock of 4.42 GHz, is currently available .

The POWER ISA v2.0 expansion of the instruction set is implemented with the POWER7 family .

OpenPOWER Foundation

In 2013, IBM established the OpenPOWER Foundation to enable the sale of POWER processors to other system manufacturers. Corresponding documentation is available from IBM. While POWER machines previously ran under the IBM AIX and OS / 400 operating systems, IBM supports Linux as the operating system on the OpenPOWER machines. Corresponding distributions are published by SUSE, Red Hat, Debian and Ubuntu, which means that the operating system and applications are also manufacturer-independent.

The Foundation discloses the specifications for processors and OpenPOWER systems. IBM has announced that in the future, POWER processors will initially appear in an OpenPOWER variant for Linux operating systems, before IBM will release corresponding processors for its own System i and AIX System p series. This underlines the importance of the OpenPOWER approach for IBM:

“This step must be seen as an attempt to establish POWER processors as a manufacturer-independent competitor to x86 products. IBM must sell higher numbers in order to finance future processor development. The targeted target market is high performance computing, which is why NVLink connections are integrated, which enable the integration of computing accelerators. "

POWER8

At the Hot Chips 25 conference in 2013, IBM presented the Power8 CPU with 12 cores. Each of the 12 cores, which can each access 512 KB L2 cache and a total of 96 MB L3 cache and 128 MB L4 cache, is capable of executing up to 8 threads simultaneously using simultaneous multithreading. Power8 is manufactured using the 22 nm process, the 12-core version has a die area of ​​650 mm² and over 4.2 billion transistors. A memory controller with 32 channels can connect up to 1 TB of DDR3-1600 RAM. The CPU clock frequency ranges from 3.02 to 4.15 GHz, depending on the configuration.

The Power8 CPUs are equipped with several high-performance connections:

  • NVLink 1.0: up to 4 Nvidia Tesla - Pascal P100 computing accelerator modules can be integrated here
  • CAPI 1.0
  • PCI Express 3.0

OpenPOWER8 systems

  • IBM:
    • S812L: 1 CPU, 2U rack system
    • S822L: 2 CPU, 2U rack system
    • S814: 1 CPU, 4U rack system
    • S824: 2 CPU, 4U rack system
  • Other manufacturers (excerpt):
    • Penguin Computing: Magna Series, 2001, 1015, 2002, 2002S
    • Raptor Computing: Talos I
    • Tyan: Palmetto (motherboard SP010GM2NR)
System E870 with up to 80 cores

POWER8 systems i / p from IBM

  • Power Systems E850 - 2 ×, 3 × or 4 × POWER8 DCM (8, 10 or 12 cores), 4U
  • Power Systems E870 - 1 × or 2 × 5U nodes, each with 4 sockets and 8- or 10-core POWER8 modules, up to 80 cores in total
  • Power Systems E880 - 1x, 2x, 3x or 4x 5U nodes, each with 4 sockets and 8- or 12-core POWER8 modules, up to 192 cores in total

POWER9

The Power9 family from IBM consists of several processor modules manufactured in a 14 nm FinFET process by Globalfoundries with 8 billion transistors on an area of ​​695 mm². They were announced at the "Hot Chip" conference in August 2016, with the first systems shipped in December 2017 for the supercomputer summit under construction at Oak Ridge National Laboratory and Sierra at Lawrence Livermore National Laboratory (LLNL), in June 2018 a cluster with IBM AC922 systems is also in operation within the MareNostrum 4 system in Barcelona.

The POWER ISA v3.0 instruction set is expanded in the POWER9 processors :

  • 128-bit quad-precision floating point and integer operations
  • 16-bit floating point conversions
  • AltiVec -3 SIMD instructions

Chip variants for 1-2 processor systems (called "Scale-Out", code name Nimbus ) and NUMA machines ("Scale-Up", code name Centaur ) are available with either up to 12 cores / 8-fold simultaneous multithreading (SMT ) or up to 24 cores / 4x SMT. The variants with 8-way multithreading are to be reserved for IBM's own Power VM platforms (System i and p).

Nimbus and Centaur differ in their main memory expansion and connection:

  • Scale-Out: 8 channels with up to 2 modules each (16 modules, 4 TB / socket), together 120 GByte / s bandwidth
  • Scale-Up: 8 channels with up to 4 modules each (32 modules, 8 TB / socket), a total of 230 GByte / s bandwidth

Each core has 32 Kbytes of data u. Instruction 1st level cache, 512 KByte 2nd level cache and 120 MB 3rd level cache common to all cores. The clock frequencies are initially shown at 2.0 to 2.6 GHz and are therefore significantly lower than with the POWER8 generation.

feature Scale-out Linux Scale-out power VM Scale-up Linux Scale-up power VM
Number of bases 1-2 1-2 4-16 4-16
Max. Number of cores 24 12 24 12
Number of threads per core / processor 4th 8th 4th 8th
DDR4 channels / modules 8/16 8/16 8/32 8/32

Power9 processors support several high performance connections:

  • A high-performance switch with 7 TB / sec bandwidth is integrated on the chip, which connects the cores, L3 cache and peripherals
  • PCI-Express 4.0 with 48 lanes and 192 GB / sec bandwidth. Version 4.0 is implemented for the first time in the POWER9 CPU
    • CAPI 2.0 over PCIe 4.0
  • up to 48 optical connections (XBus) with 25 GB / sec bandwidth, in total 300 GB / sec
    • NVLink 2.0 over 25 G / s for connecting Nvidia computing accelerators.
    • OpenCAPI 3.0 over 25 G / s, intended for the connection of further accelerator chips
  • Accelerators for GZIP, AES and random numbers are built into the chip and included in the POWER ISA 3.0.
  • Using the integrated NVLink 2.0 interfaces, up to 4 (IBM AC922) or 6 (IBM S922LC) Nvidia Tesla computing accelerators (Volta Generation - V100) can be integrated into a 2-socket system.

OpenPOWER9 systems

Three IBM processor packages are available in 01/2018:

  • Sforza: 50 mm × 50 mm, FC-PLGA, 4 DDR4, 48 PCIe lanes and 1 XBus 4B
  • Monza: 68.5 mm × 68.5 mm, FC-PLGA, 8 DDR4, 34 PCIe lanes and 1 XBus 4B, 48 OpenCAPI lanes
  • LaGrange: 68.5 mm × 68.5 mm, FC-PLGA, 8 DDR4, 42 PCIe lanes and 2 XBus 4B, 16 OpenCAPI lanes

The following manufacturers had OpenPOWER-9 systems on offer at the time of POWER9 product launch:

  • IBM: Power System AC922 (Witherspoon) with Monza modules
  • Raptor Computing Systems: Talos II with Sforza modules
  • Penguin Computing: Magna PE2112GTX with LaGrange modules

IBM Scale Out POWER9 Systems

In mid-February 2018, IBM presented the first 6 systems that, in addition to Linux, can also use the in-house operating systems AIX and System i or OS / 400 . These are 1–2 socket systems of the scale-out variants with a main memory expansion of up to 2 TB per socket. The housings are available with 2 or 4 height units, the 4U housings are supplied with up to 12-core CPUs, the 2U with up to 10-core CPUs. 2 variants are certified for SAP HANA applications:

model Cores Height / base Operating systems R.A.M. IO
L922 8/10/12 2U / 1-2S Linux 4TB 5 × PCIe G4 (4 CAPI 2.0), 4 × PCIe G3
S914 4/6/8 4U / 1S AIX, IBM i, Linux 1TB 2 × PCIe G4 (4 CAPI 2.0), 6 × PCIe G3
S922 4/8/10 2U / 1-2S AIX, IBM i, Linux 4TB 5 × PCIe G4 (4 CAPI 2.0), 4 × PCIe G3
S924 8/10/12 4U / 2S AIX, IBM i, Linux 4TB 5 × PCIe G4 (4 CAPI 2.0), 6 × PCIe G3
H922 4/8/10 2U / 1-2S HANA, AIX, IBM i 4TB 5 × PCIe G4 (4 CAPI 2.0), 6 × PCIe G3
H924 8/10/12 4U / 2 S HANA, AIX, IBM i 4TB 5 × PCIe G4 (4 CAPI 2.0), 6 × PCIe G3
E950 8/10/11/12 4U / 2-4S AIX, IBM i, Linux 16TB / 4x16 DDR4 DIMMs 8x16 + 2x8 PCIe G4, (4 CAPI 2.0, 4 NVLink), 1x8 PCIe G3, 4 NVMe
E980 8/10/11/12 4 "nodes" with 5U, 1 SCU 2U / 4-16S AIX, IBM i, Linux 64TB / 16x8 CDIMMs (TFF or SFF) 4x8x16 PCIe G4, 4x4 NVMe, 32 accelerator links (CAPI 2.0 or NVLink or OpenCAPI)

POWER10

At the HC32 2020 hot chips conference, IBM announced systems with Power10 for the second half of 2021. The processors are to be manufactured in 7 nm structures and comply with Power ISA v3.1, which is disclosed as part of OpenPOWER.

Individual evidence

  1. ↑ Hugh Blemings: The Next Step in the OpenPower Foundation Journey, August 20 of 2019.
  2. ↑ Mark Mantel: Processor ISA Power: OpenPower Foundation presents an open license model. In: Heise online . 17th February 2020 . Retrieved February 18, 2020 .; Quote: "In the future, chip manufacturers can develop and sell power processors without having to pay license fees to the OpenPower Foundation."
  3. ↑ The Register: IBM pumps Unix line full of Power5 + (English) from October 4, 2005
  4. ^ The Register: IBM begins third phase of Power5 + journey (English) from July 11, 2006
  5. ↑ Power6 Fact Sheet, May 21, 2007.
  6. ↑ Heise online : Technical details on IBM's POWER7 processors and servers
  7. ↑ IBM : Power Hardware
  8. ↑ Heise online : IBM expands server line with Power7 + processor
  9. ↑ a b IBM Portal for OpenPOWER. Retrieved January 10, 2018 .
  10. ↑ Home - OpenPOWER. Retrieved January 10, 2018 .
  11. ↑ IBM Power Systems S814 and S824 Technical Overview and Introduction. Retrieved January 10, 2018 .
  12. ↑ POWER8 - Micro Architectures - IBM. Retrieved January 10, 2018 .
  13. ↑ IBM Power System S822LC for High Performance Computing Introduction and Technical Overview. Retrieved January 10, 2018 .
  14. ↑ IBM Power Systems S814 and S824 Technical Overview and Introduction. Retrieved January 10, 2018 .
  15. ↑ Magna OpenPOWER Server. Retrieved January 10, 2018 .
  16. ↑ TYAN's OpenPower Customer Reference System Now Available. Retrieved January 10, 2018 .
  17. ↑ http://www.redbooks.ibm.com/redpapers/pdfs/redp5137.pdf
  18. ↑ https://www.heise.de/ix/meldung/IBM-POWER9-Server-zu-Weihnachten-3910888.html
  19. ↑ https://www.nextplatform.com/2018/06/13/bsc-fires-up-power9-v100-hybrid-compute-on-marenostrum-4/
  20. ↑ https://www.extremetech.com/extreme/234413-ibm-details-next-gen-power-9-will-take-the-fight-to-intels-data-center-strongholds
  21. ↑ https://cdn2.hubspot.net/hubfs/652102/Documents/POWER9-Features-and-Specifications.pdf
  22. ↑ https://en.wikichip.org/wiki/ibm/microarchitectures/power9
  23. ↑ https://openpowerfoundation.org/wp-content/uploads/2016/11/Jeff-Stuecheli-POWER9-chip-technology.pdf
  24. ↑ see also https://www.extremetech.com/computing/237734-google-puts-intel-on-notice-looks-forward-to-using-non-intel-chips-within-its-cloud
  25. ↑ https://www.ibm.com/de-de/marketplace/power-systems-ac922/details
  26. ↑ https://www.raptorcs.com/
  27. ↑ https://www.heise.de/ix/meldung/IBM-Server-mit-POWER9-3966886.html
  28. ↑ http://www.theregister.co.uk/2018/02/14/ibm_power9_servers/
  29. ↑ Christof Windeck: IBM POWER10 for servers with up to 960 threads and clusters with 2 PByte RAM. In: Heise online . 17th August 2020 . Retrieved August 19, 2020.

Web links

  • Timo Schöler: Close-up: IBM Power. (PDF, 404 KByte), an overview of developments in IBM's Power CPUs in recent years, detailed presentation of the technologies used in the Power5 (+) CPU (2005)