Multiple structuring

Among multiple patterning ( English multiple patterning ) are in the semiconductor technology , various patterning methods summarized very dense and fine patterns for fabrication. Most of the processes are based on photolithographic structuring (usually the demanding immersion lithography ) with double the pitch of the desired structures. In principle, the structure sizes that can be achieved can be halved compared to simple structuring; in the case of immersion lithography, the structure sizes that can be achieved are already below the actual resolution limit of the wavelength used for imaging.

The easiest way is to double patterning (English double patterning ), are being summarized under this term various techniques, see below . The double structuring was introduced in the semiconductor industry in the middle to the end of the 2000s at the 32 nm technology node , since with the production processes of the time ( 193 nm photolithography and immersion lithography ) the imaging of photoresist structures at a half pitch of 45 nm is no longer sufficient could be shown in focus. Since the next generation of photolithography techniques were too expensive at the time or were not yet available for high-volume production, the double structuring enabled a relatively “simple” and “more cost-effective” production of structures with higher structure densities with conventional photolithography systems . The technique has been used in various forms since then. The methods of multiple structuring usually represent extensions or combinations of individual techniques that are already used in double structuring.

Multiple structuring belongs to the group of resolution enhancement techniques (RET), which are used for structure sizes below the light wavelength (193 nm).

Basic approaches

Multiple exposure

Double exposure: photoresist coating; first exposure; second exposure; development

Multiple exposure is a special photolithographic method in which a sequence of at least two separate exposure steps are carried out using different photo masks and a final etching step. The simplest form of multiple exposure is double exposure with a final etch, which can be divided into two forms:

1. two exposure steps on the same photoresist layer with different photomasks (sequence: photoresist application, exposure 1, exposure 2, development) and final etching
2. two separate complete photolithography steps with two photoresist layers including development after the first exposure (sequence: photoresist application 1, exposure 1, development 1, photoresist application 2, exposure 2, development 2) and final etching

This technology is generally used for structural patterns that look very different or have incompatible structural densities or distances. Such patterns can, for example, be broken down into two patterns with different orientations (e.g. rotated by 90 °).

Overlay offset of line structures during double exposure

The problem with the use of multiple exposure is the overlay offset that occurs between the structures or structural parts of the different exposure steps. The overlay offset occurs because the components of the optical system that have changed between the two exposure steps can never be perfectly aligned with each other (example causes: mask alignment, wafer topography, focus, exposure dose, thermal expansion, etc.).

A variant of the multiple exposure approach is the so-called " resist freezing " (German: photoresist solidification, English also litho, freeze, litho, etch , LFLE). This technique allows the existing photoresist layer to be coated with a second photoresist layer. The JSR Corporation demonstrated this approach for the production of 32 nm wide lines and spaces. The solidification was achieved by surface hardening of the first lacquer layer.

Direct write electron beam lithography is inherently a multiple exposure technique because the electron beam is shaped differently and projected onto the photoresist at multiple locations.

Double exposure and double etching

The double exposure and Doppelätzung (Engl. Double exposure, double etch , DEDE, also DE / DE or DE², sometimes English. Litho etch litho etch , LELE called) is another double patterning technique that is already being used. In contrast to the double exposure described above, an etching process follows after each exposure step, in which the pattern of the respective exposure is transferred into the material located under the photoresist. This can be the layer actually to be structured, e.g. B. polysilicon for later gate electrodes, as well as auxiliary layers that serve as hard masks , be. As a result of this sequence of exposure, etching, exposure and etching, a structured layer is obtained in which the structure patterns of the first and second photomask are combined.

The possibility of fixing the structures of the first exposure step in a further layer (the hard mask) is a major advantage of the DEDE approach compared to simple double exposure. The interactions that occur between the images of both exposure steps in the same photoresist layer can be excluded with the DEDE approach, and higher structure densities can be produced in this way than with double exposure alone.

By nesting the two partial patterns, the structure density can theoretically be increased indefinitely; the half-pitch is inversely proportional to the number of partial patterns used. For example, a 25-nm half-pitch pattern can be created by two 50-nm half-pitch patterns, three 75-nm half-pitch patterns, or four 100-nm half-pitch patterns. The downsizing of the structures will most likely require the help of other techniques such as chemical shrinks , thermal reflow or shrink assist films . In practice, however, there are limits to this methodology. B. increased variation in manufacturing and higher costs with each additional stage.

With this technique, too, further sub-processes can be distinguished with regard to the number of hard mask and planarization layers, the type of photoresist used, the masking approach chosen (production of lines or trenches in the hard mask), etc. In the following, two process sequences with and without the use of a hard mask are described as examples.

Line doubling approach

DEDE structuring according to the line doubling approach with hard mask

With the classic DEDE structuring, cf. On the right, an additional sacrificial layer is first deposited on the material / substrate to be structured, which later serves as a hard mask. This hard mask is etched after a normal photolithography step (resist application, exposure and development of the photoresist / resist). The structure of the photomask is transferred into the hard mask layer. After the first photoresist mask has been removed, the second photolithographic structuring with a different photomask and renewed etching of the hard mask follow. The result is a pattern that is composed of the structures of the new photoresist layer and the hard mask and can be transferred to the underlying target layer or target layer stack by a subsequent anisotropic etching process.

This technology theoretically enables the structure density to be doubled, as demonstrated by the Interuniversity Microelectronics Center (IMEC, Belgium) for structuring the gate levels with a 32 nm half-pitch process. Similar to the double exposure, the two partial structuring also take place more or less independently of one another with this approach. The tolerances that occur during manufacture between the second photoresist pattern and the first hard mask pattern result in an additional variation in the distance.

Trench doubling approach

DEDE structuring using the trench doubling approach with a hard mask

The adjacent picture for the production of closely spaced trench structures shows a DEDE approach without a hard mask. As can be seen, no sacrificial layer is applied and the pattern from the first exposure step is transferred directly into the target layer by etching the underlying material. This process sequence is then repeated and a structured layer is again obtained that combines the patterns of the two exposure steps.

Self-aligned (spacer) double pattering (SaDP)

SaDP process: a) photolithographic structuring; b) Si ₃ N ₄ deposition; c) Spacer production by anisotopic etching; d) removal of the resist mask; e) anisotropic etching of the underlying layer (poly-Si); f) Removal of the spacers

Thin structured layers on the side wall of existing structures are referred to as spacers . They are formed by conformal deposition, i.e. uniformly on all surfaces including the side walls, a layer on a previously structured surface and subsequent anisotropic etching (material removal perpendicular to the surface) of the layer. This process sequence creates two new structures: one spacer each on the left and right side of the original structure. The original line density can be doubled through appropriate process conditions (especially the deposited layer thickness). The spacer technology thus enables narrow gate structures to be produced with half the original lithographic line spacing.

The spacer approach is unique in that with a single lithographic exposure, the line width can be halved regardless of the sequence of spacer formation and the structure transfer processes. In this way the serious problem of very tight overlay tolerances between successive exposures is avoided. The necessary control and homogeneity of the layer thickness over the entire wafer and independent of the local structure densities, however, represent a challenge that should not be neglected in high-volume production.

Hard mask materials such as silicon nitride or silicon dioxide are generally used as spacer materials . After etching, they show structures of better quality than photoresist masks, which are usually characterized by higher edge roughness.

In addition to layer thickness control, the most important issues in the spacer approach are:

1. Do the spacers remain after the material of the original structure to which they are attached?
2. Is your profile acceptable?
3. Will the underlying material be attacked when removing the spacers?

The structure transfer is complicated in that a little of the underlying material is also removed during the spacer production (overetching). This is necessary so that no material remains in areas that should remain free. However, this approach leads to a slightly higher topography of the substrate in the free areas protected by the spacer or dummy gate. This leads to additional challenges in production for subsequent process steps, the fine-tuning of the electrical transistor parameters and the structuring itself if the SaDP approach should be carried out several times.

Two-tone process

Two-tone photoresists

Two-tone photoresist: The lowest and highest doses from a single exposure result in the insolubility of the photoresist, while the photoresist can be removed after exposure with a medium dose of developer.

A few years ago called Zweitonfotolacke were (Engl. Dual-tone photo-resist ) developed that allow, (Engl. After exposure / imaging of a single line structure line ) to create two adjacent line structures. Initial demonstrations of this technology used photoresists that were inherently insoluble in the developer (which also did not change the exposure with low doses) and in which at the same time high doses caused a crosslinking reaction that also made them insoluble. Alternatively, at high doses, a photo base generator can create “acid quenchers” that counteract the reaction that makes the photoresist soluble. Due to the simplicity and economy of this approach, the photolithographic capabilities of current photoresists could be expanded.

Two-tone development

Two-tone development: In two development steps , the photoresist areas with the highest and lowest levels are removed so that the areas with the medium dosage remain as a mask.

Two- tone development (DTD) is similar to the two- tone photoresist technology described above and also enables the production of duplicated structures without additional exposure. One example is a process developed by Fujifilm . In contrast to the two-tone photoresist, however, the photoresist is developed twice. In the first step, a developer (for example the conventionally used TMAH ) removes the areas exposed to a high radiation dose. The second step uses a chemically different solvent, such as water or an organic solvent, which removes the unexposed areas or areas exposed with a low dose of radiation. The solvents used are selected depending on the photoresist chemistry and the type of photoresist, among other things, and can differ significantly from the chemicals mentioned. Regardless of which solvents are used, the result of a successful process is that the areas exposed with medium dosage remain in place, in which each edge is produced by a partial development process. A central challenge here is not only to show process windows for the individual developments, but also to ensure sufficient window overlap. To date (2010), such an overlap has only been shown in simulations and not experimentally.

Combinations

Structure quadrupling with double spacer structuring: Deposition of the first spacer; Etching the first spacers; Etching the first and second carrier layers (A and B); Deposition of the second spacer; Etching of the second spacer, etching of the second carrier layer (B)

In addition to double structuring, the multiple spacer approach is currently the most widely published multiple structuring methodology that can be practiced in many forms. But it is also possible to combine two or more of the approaches mentioned above. For example, the use of a two-tone photoresist with a pitch-halved acid profile in combination with a two-tone development that dissolves the highest and lowest acid concentrations. Theoretically, this would enable the pitch resolution to be improved by a factor of 8, for example scaling a 40 nm wide half pitch to 5 nm. In addition, a repeated spacer approach could improve the resolution by a factor of 16, resulting in a 40 nm wide half-pitch could be reduced to 2.5 nm. The practical implementation, especially in the volume production of such theoretical approaches, is demanding and has so far hardly / not been shown even on a laboratory scale.

2D layout considerations

The increase in structure density for 2D patterns is very much dependent on the type of pattern. For example, contact fields, i.e. larger areas in which there are a large number of holes for contacting the source, drain and gate, have an optimal packing density for double structuring as rectangular fields , whereas hexagonal arrangements are optimally suited for triple structuring - here is approximately twice or three times better use of space was achieved. In the case of 2D layouts, errors occur in compliance with the design rules for the double structuring if odd periods of the smallest distances are present. This can be solved by loosening the size of one of these distances to a value at which both structures can be imaged in the same exposure step. On the other hand, the triple structuring conforms to an odd period, but it is again not suitable for the production of two opposing pairs of line ends in which the corner-to-corner distance is less than the distance of a single structuring. This in turn conforms to a four-way structure. The improvement of the structure density using multiple structuring is therefore highly dependent on the respective pattern. Often, simple design changes or relaxed size specifications in one direction can avoid the effort and costs associated with more complex and expensive multiple structuring processes.

Applications

Due to its rather simple application, that is, without the need to change the industrial infrastructure , simple forms of multiple structuring are likely to encounter only minor technical or economic barriers in the future. Despite concerns about cost and throughput, these techniques have received more attention and interest recently (as of 2010). This also has to do with the delays in the next generation of lithography techniques such as EUV and nano-embossed lithography .

Multiple structuring can also be used in high bias processes (e.g. photoresist trimming by line widths or photoresist reflow to reduce trench widths ) in order to reduce the defect density for a design pitch of 2 × or smaller. In view of the increasing resolution of the photolithography systems, which generally leads to a higher defect density on the wafers, this is a major advantage.

Photolithography

The double structuring has been used for several years by many larger semiconductor manufacturers ( Intel , Globalfoundries , TSMC etc.) for the production of gate structures, for example Intel for logic products in 65 nm and 45 nm technology. For example, while a DEDE variant is used, a dense line pattern is fixed in a hard mask in the first partial step and be "tailored" in the second step, these lines (engl. Cut ). Structures with very rectangular line ends are typical of such a process. With a single photolithography process, this end shape cannot be achieved due to diffraction effects with the same systems and structure sizes - not even if OPC techniques are used. The extrapolation from double to multiple structuring has already been considered, but is still limited by the problem of cost control. Furthermore, although the advantages of multiple structuring in terms of resolution, depth of field and lithographic defect sensitivity are understood, there are currently still questions regarding the control of the process budget increase and the maintenance of a good yield.

Future logic products could also be manufactured through multiple structuring using 193 nm immersion lithography. Intel showed research results for 11 nm technology (corresponds to a pitch of 20–22 nm), in which 5 exposure steps with a total of 5 masks were used. An exposure with spacer structuring was used to achieve a further pitch distribution. The remaining four exposures, however, were used again for trimming the pitch-split lines. This is worth mentioning because next-generation lithography processes such as EUVL or maskless direct electron beam lithography would still require a second exposure step for cutting off the lines.

The IMEC has indicated that in the event that EUV lithography is still not ready for use, the quadruple structuring (with narrower overlay specifications) could be used for the production of future components.

At the 2010 Flash Memory Summit it was estimated that immersion lithography with multiple structuring would be used to scale NAND flash memories to structure widths below 20 nm within a few years .

Electron beam lithography

As mentioned earlier, electron beam lithography is inherently a multiple exposure technique. However, electron beam lithography would ultimately also require at least two connected exposure steps (through secondary electron scattering), for example in the production of X-ray zone plates with a half-pitch of 15 nm. In fact, it is possible that the double structuring even for the sub-12 nm half-pitch range cannot be sufficient, not even with electron beam lithography. In this case, multiple structuring would be necessary.

Individual evidence

1. ↑ Tokuyuki Honda, Yasuhiro Kishikawa, Yuichi Iwasaki, Akinori Ohkubo, Miyoko Kawashima, Minoru Yoshii: Influence of resist blur on ultimate resolution of ArF immersion lithography . In: Journal of Microlithography, Microfabrication, and Microsystems . tape 5 , 2006, p. 043004 , doi : 10.1117 / 1.2397018 .
2. ↑ Carlos Fonseca, Mark Somervell, Steven Scheer, Wallace Printz, Kathleen Nafus, Shinichi Hatakeyama, Yuhei Kuwahara, Takafumi Niwa, Sophie Bernard, Roel Gronheid: Advances and challenges in dual-tone development process optimization . SPIE, 2009, p. 72740I , doi : 10.1117 / 12.814289 .
3. ↑ cf. Michael Lercel: 2006 Lithography Update. (PDF) (No longer available online.) In: ITRS Winter Conference 2006. 2006, p. 9 , archived from the original on July 15, 2014 ; Retrieved May 12, 2013 . Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.  
4. ↑ Yayi Wei, Robert L. Brainard: Advanced Processes for 193-nm Immersion Lithography (=  SPIE Press monograph . Volume 189 ). SPIE Press, Bellingham 2009, ISBN 978-0-8194-7557-2 , pp. 215 .
5. ↑ S. Kusumoto et al .: Double Patterning with Resist Freezing Process. In: Workshop on Optical Lithography at 22nm and 16nm. May 15, 2008 ( Presentation slides as PDF ( memento of the original from July 14, 2014 in the Internet Archive ) Info: The archive link has been inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this note. ). 
6. ↑ Mark LaPedu: JSR demos 'freezing material' for 22-nm production . eetimes, March 13, 2008.
7. ↑ Rasit Onur Topaloglu, Peng Li: Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits . Bentham Science Publishers, 2011, ISBN 978-1-60805-074-1 , pp. 11-13 .
8. ↑ cf. M. Maenhoudt, D. Vangoidsenhoven, T. Vandeweyer, R. Gronheid, J. Versluijs, A. Miller: Double Patterning process development at IMEC. (PDF) (No longer available online.) In: Litho Forum 2008. 2008, p. 4 , archived from the original on July 14, 2014 ; Retrieved May 12, 2013 . Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.  
9. ↑ cf. Michael Lercel: 2006 Lithography Update. (PDF) (No longer available online.) In: ITRS Winter Conference 2006. 2006, p. 8 , archived from the original on July 15, 2014 ; Retrieved May 12, 2013 . Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.  
10. ↑ Double patterning lithography ( Memento of the original dated December 11, 2010 in the Internet Archive ) Info: The  archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. . IMEC, 2007.
11. ↑ Xuefeng Hua, S. Engelmann, GS Oehrlein, P. Jiang, P. Lazzeri, E. Iacob, M. Anderle: Studies of plasma surface interactions during short time plasma etching of 193 and 248 nm photoresist materials . In: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures . tape 24 , 2006, pp. 1850-1858 , doi : 10.1116 / 1.2217973 .
12. ↑ Yang-Kyu Choi, Ji Zhu, Jeff Grunes, Jeffrey Bokor, Gabor. A. Somorjai: Fabrication of Sub-10-nm Silicon Nanowire Arrays by Size Reduction Lithography . In: J. Phys. Chem. B . tape 107 , no. 15 , 2003, p. 3340-3343 , doi : 10.1021 / jp0222649 .
13. ↑ Patent US6114082 : Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same. Released September 5, 2000 . ‌
14. ↑ Soyoung Song, Shoichi Yokoyama, Shigeru Takahara, Tsuguo Yamaoka: Novel dual-mode photoresist based on decarboxylation by photogenerated base compound Novel dual-mode photoresist based on decarboxylation by photogenerated base compound . In: Polymers for Advanced Technologies . tape 9 , no. 6 , 1998, pp. 326-333 , doi : 10.1002 / (SICI) 1099-1581 (199806) 9: 6 <326 :: AID-PAT785> 3.0.CO; 2-5 .
15. ↑ Xinyu Gu et al: A New Materials-based Pitch Division Technique A New Materials-based Pitch Division Technique . In: Journal of Photopolymer Science and Technology . tape 22 , no. 6 , 2009, p. 773-781 , doi : 10.2494 / photopolymer.22.773 .
16. ↑ Yayi Wei, Robert L. Brainard: Advanced processes for 193-nm immersion lithography . SPIE Press, 2009, ISBN 978-0-8194-7557-2 , pp. 249–251 (Section 9.6 Novel Approaches ).
17. ^ Katherine Derbyshire: Double development offers simpler double patterning . In: Solid State Technology . tape 51 , no. 5 , 2008, p. 18-20 ( HTML ).
18. ^ Andrew Carlson, Tsu-Jae King Liu: Negative and iterated spacer lithography processes for low variability and ultra-dense integration . tape 6924 . SPIE, 2008, p. 69240B , doi : 10.1117 / 12.772049 .
19. ↑ B. Degroote et al .: Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density . In: Microelectronic Engineering . tape 84 , no. 4 , 2007, p. 609-618 , doi : 10.1016 / j.mee.2006.12.003 .
20. ↑ Yang-Kyu Choi: Sub-lithographic patterning technology for nanowire model catalysts and DNA label-free hybridization detection . tape 5220 . SPIE, 2003, p. 10-19 , doi : 10.1117 / 12.505409 .
21. ↑ Beom-Seok Seo et al: Double patterning addressing imaging challenges for near- and sub-k . SPIE, 2009, p. 73791N-73791N-10 , doi : 10.1117 / 12.824300 .
22. ↑ D. Vogler: Intel product launch event yields more insight into its manufacturing strategy  ( page no longer available , search in web archives )  Info: The link was automatically marked as defective. Please check the link according to the instructions and then remove this notice. .  Solid State Technology (now ElectroIQ), November 2007.
23. ↑ C. Auth et al.: 45nm high-k + metal gate strain-enhanced transistor . In: Intel Technology Journal . Vol. 12, No. 2 , 2008, p. 77-86 , doi : 10.1109 / VLSIT.2008.4588589 ( PDF ). PDF ( Memento of the original from July 10, 2012 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.  
24. ↑ Intel 45 nm process at IEDM ( Memento from March 24, 2009 in the Internet Archive )
25. ↑ Yan Borodovsky: ArF lithography extension for critical layer patterning. LithoVision 2010, February 21st, San. Jose, CA / USA (2010). Quoted from: Intel Sr. Fellow Recommends Complementary Solutions for ArF Extension ( Memento of the original from July 14, 2011 in the Internet Archive ) Info: The  archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. . Nikon Precision Inc. 2010.
26. ↑ Peter Clarke: EUV litho keeps progressing, keeps slipping . EETimes, June 9, 2010.
27. ↑ Garry Tessler: Enabling MLC Flash SSD In Enterprise Storage. 2010 Flash Memory Summit (presentation, presentation slides online ( memento from July 11, 2011 in the Internet Archive ))
28. ↑ Erik Anderson, Weilun Chao: Double exposure makes dense high-resolution diffractive optics . In: SPIE Newsroom . 2007, doi : 10.1117 / 2.1200702.0599 .
29. ↑ Weilun Chao, Jihoon Kim, Senajith Rekawa, Peter Fischer, Erik Anderson: Hydrogen silsesquioxane double patterning process for 12nm resolution x-ray zone plates . In: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures . tape 27 , 2009, p. 2606-2611 , doi : 10.1116 / 1.3242694 .
30. ↑ Weilun Chao, Erik H. Anderson, Peter Fischer, Dong-Hyun Kim: Toward sub-10-nm resolution zone plates using the overlay nanofabrication processes . In: Proc. SPIE . tape 6883 , 2008, p. 688309 , doi : 10.1117 / 12.768878 .