Tensilica

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Tensilica Inc.
legal form subsidiary company
founding 1997
resolution 2013
Reason for dissolution Takeover by Cadence
Seat San Jose (California)
management Chris Rowen, Jack Guedj
Branch Semiconductor technology company
Website https://ip.cadence.com

Tensilica was a company based in Silicon Valley , the IP cores developed. In 2013 Tenssilica was acquired and made a division of Cadence Design Systems . The dataplane processors (DPUs) developed there combine the strengths of processors ( CPUs ) and digital signal processors ( DSPs ) through user-defined logic. This makes them suitable for processing data-intensive tasks.

Tensilica is known for its customizable microprocessor cores like the configurable processor Xtensa . Other products include: HiFi audio and voice DSPs with a software library of over 225 codecs from Cadence and over 100 software partners; Vision DSPs, which handle complex algorithms in imaging, video, computer vision and neural networks and the  ConnX family of baseband DSPs from the Dual- MAC- ConnX D2 to the 64- MAC- ConnX -BBE64EP.

Tensilica was founded in 1997 by Chris Rowen and Harvey C. Jones in Santa Clara (California) , who was also one of the founders of MIPS Technologies and was initially started by several former employees of other processor manufacturers and Electronic Design Automation  (EDA) software manufacturers from Silicon Valley. The co-developer of the MIPS architecture,  Earl Killian, was also employed there as a leading software architect. On March 11, 2013, Cadence Design Systems  announced it would buy Tensilica for approximately $ 380 million in cash. In April 2013, Cadence acquired Tensilica for approximately $ 326 million in cash.

Products

Cadence Tensilica develops IP cores for integrated circuits such as  SoCs for  its licensees for embedded systems , especially for use in mobile devices, home entertainment and communication. Tensilica IP cores are supplied as synthesizable register transfer data (RTL models) for easy integration into chip designs  .

Configurable cores of the Xtensa series

An Xtensa processor can range from a small, energy-saving microcontroller  with no cache memory to a high-performance 16-way SIMD processor, triple  VLIW - DSP core or 1- TMAC neural network processor. All Cadence standard DSPs are based on the Xtensa architecture.

IP core processor manufacturers such as Tensilica typically offer their licensees the choice between many implementation details of the IP core: cache size, processor bus width, data and instruction RAM, memory management and interrupt control. The Xtensa architecture from Cadence offers the user-adaptable instruction set as an essential function  .

Using the customization tools provided, customers can extend the basic Xtensa command set themselves by defining new custom commands. Extensions can include SIMD instructions, new register files and additional data transmission interfaces for multiprocessor communication. After the final processor configuration has been created and submitted, the Tensilica processor generator creates the configured Xtensa IP core, the processor design kit and the software development kit. This process is highly automated so that designers can quickly experiment with the various commands they have created to test both performance improvements and performance degradation among the possible alternatives.

The processor kit contains the necessary elements to integrate the configured IP core into the customer's chip design development environment: the hardware description of the core (in synthesizable register transfer language ( RTL ) or physical post-layout form), timing and I / O restrictions, requirements for technology-specific RAMs / caches / FIFOs. The software kit is based on an Eclipse (IDE)  based  integrated development environment  and used by the  GNU Compiler Collection  derived toolchain : C / C ++ - compiler, assembler, linker, debugger. An instruction set simulator enables customers to begin application development before the actual hardware is available.

The instruction set of the Xtensa

The Xtensa instruction set was developed to meet the various requirements of dataplane processing. This 32-bit architecture offers a compact 16- and 24-bit instruction set with non-modal switching for maximum power efficiency and performance. The basic instruction set has 80 RISC instructions and a 32-bit ALU  with up to 64 universal 32-bit registers  and six special registers.

HiFi audio and Voice DSP IP

Simplified block diagrams of the HiFi audio engine and Xtensa LX.
  • HiFi Mini Audio DSP - The smallest DSP core with the lowest power consumption for speech output and speech recognition
  • HiFi 2 Audio DSP - This highly efficient DSP core offers the most powerful MP3 processing.
  • HiFi EP Audio DSP - Upper-class HiFi-2 with extended optimizations for DTS Master Audio, improved pre- and post-processing of the voice and improved cache memory subsystem
  • HiFi 3 Audio DSP - Full 32-bit processing makes this DSP extremely efficient for many of the audio enhancement algorithms, wideband speech codecs, and multi-channel audio.
  • HiFi 3z Audio DSP - energy-efficient DSP for object-based audio, super-broadband speech codecs and automatic speech recognition with a neural network
  • HiFi 4 DSP - 2 × HiFi 3 performance for DSP-intensive applications including new object-based multi-channel audio standards

Vision DSPs

  • Vision P5 DSP with 4 to 100 times the performance of a conventional mobile CPU + GPU system at a fraction of the energy to performance ratio
  • Vision P6 DSP with four times the performance of the Vision P5 DSP for demanding image and computer video applications.
  • Vision C5 DSP, with 1 TMAC per second computing power, in order to be able to carry out computing tasks of a neural network without additional hardwired accelerators.

adoption

AMD TrueAudio, an audio DSP that u. a. in the Playstation 4 , in the AMD APUs of the “Kaveri” desktop and in some AMD dGPUs, is based on the Cadence Tensilica HiFi-EP-Audio-DSP.

Microsoft HoloLens uses a specially manufactured TSMC 28 nm coprocessor with 24 Tensilica DSP cores with around 65 million logic gates, 8 MiB SRAM and an additional layer of 1 GB low-power DDR3 RAM.

Espressif ESP8266  Wi-Fi IoT SoC integrates the Tensilica Diamond on a standard 106 micro 32-bit controller processor core, which Espressif calls L106 .

Spreadtrum licensed a HiFi DSP for smartphones.

VIA Technologies uses a HiFi DSP in the SoC for set-top boxes, tablets and mobile devices.

Realtek has built chips for mobile devices and PC products on the hi-fi audio DSP platform.

Tensilica's over 80 leading semiconductor manufacturers and OEM system customers use HiFi audio DSPs in their chip designs.

history

  • In 1997 Tensilica was founded by Chris Rowen.
  • In 2002 Tensilica released support for flexible command encoding lengths known as FLIX.
  • In 2013, Tensilica was acquired by Cadence Design Systems.

Name of the company

The brand name Tensilica is a combination of the words Tensile  (= stretchable, expandable) and Silica  (= silicon ) , the element  from which  integrated circuits  are made.

Individual evidence

  1. ↑ Harvey Jones, Tensilica Inc: Profile & Biography. Retrieved May 12, 2018 .
  2. ^ Technical Advisory Board , Stretch . November 26, 2010. "Earl ... He is the former Chief Architect of Tensilica and Silicon Graphics MIPS division, ..." 
  3. ↑ SEMbyotic - sembyotic.com: Cadence to Acquire Tensilica | Cadence IP. Retrieved May 12, 2018 .
  4. ↑ SEMbyotic - sembyotic.com: Cadence Reports First Quarter 2013 Financial Results and Completes Acquisition of Tensilica | Cadence IP. Retrieved May 12, 2018 .
  5. ↑ New Cadence Tensilica Vision P5 DSP Enables 4K Mobile Imaging with 13X Performance Boost and 5X Lower Energy. Retrieved May 12, 2018 .
  6. ↑ Cadence Announces New Tensilica Vision P6 DSP Targeting Embedded Neural Network Applications. Retrieved May 12, 2018 .
  7. ↑ Cadence Unveils Industry's First Neural Network DSP IP for Automotive, Surveillance, Drone and Mobile Markets. Retrieved May 12, 2018 .
  8. ^ Everything You Wanted to Know About AMD TrueAudio . In: Maximum PC . October 8, 2013. Archived from the original on July 11, 2014. Retrieved July 6, 2014.
  9. ↑ Microsoft's HoloLens secret sauce: A 28nm customized 24-core DSP engine built by TSMC . ( theregister.co.uk [accessed May 12, 2018]).
  10. ↑ Spreadtrum Licenses Tensilica HiFi Audio / Voice DSP. Retrieved May 12, 2018 .
  11. ↑ Customer Spotlight: VIA Technologies Licenses Cadence Tensilica HiFi Audio / Voice DSP. Retrieved May 12, 2018 .
  12. ↑ Realtek Licenses Cadence's Tensilica HiFi Audio / Voice DSP IP Core. Retrieved May 12, 2018 .

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