Peripheral component interconnect

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32 bit PCI slot
32 bit PCI network card: on the left the standardized sheet metal with the connection socket, below the contacts for the expansion slot directly on the circuit board
Ethernet card (NIC) for the PCI-X slot.
PCI-Express and PCI slots on a PC motherboard : from top to bottom: PCI-Express x4, x16, x1, x16 and conventional PCI

Peripheral Component Interconnect , usually abbreviated to PCI , is a bus standard for connecting peripheral devices to the chipset of a processor .

There are numerous variants and areas of application of the standard ( PC , industry , telecommunications ). The best-known variant is mainly used in the PC environment and is officially called PCI Conventional . Practically every IBM PC-compatible computer built since around 1994 is usually equipped with two to seven slots for PCI cards (with the exception of miniature and mobile versions). Newer computers from Apple (from 1995 to 2005, later PCI Express ) and workstations from Sun also have a PCI bus. All sorts of cards from many manufacturers can be inserted into the slots, including network cards , modems , SCSI cards, sound cards , (older or second) graphics cards , cards with a parallel printer connection or with additional USB slots. This allows a PC to be easily adapted to special needs.

Version 1.0 of the standard was defined by Intel in 1991. Intel supported the V ESA L ocal B us not (VLB), as it specifically to the 486 was designed architecture and offered less throughput. In contrast, the PCI bus can be used in any architecture.

There are now three different standards:

Conventional PCI
  • PCI 1.0, proposed by Intel in 1991
  • PCI 2.0, introduced by PCI-SIG in 1993
  • PCI 2.1, adopted in June 1995
  • PCI 2.2, adopted in January 1999
  • PCI 2.3, adopted in March 2002
  • PCI 3.0, adopted in April 2004
PCI Extended (PCI-X)
  • PCI-X 1.0, adopted in September 1999
  • PCI-X 2.0, adopted in July 2002
PCI Express (PCIe or PCI-E)
  • originally known as 3GIO
  • PCI Express 1.0, adopted July 2002
  • PCI Express 1.1
  • PCI Express 2.0, adopted in 2007
  • PCI Express 2.1
  • PCI Express 3.0, adopted in 2010
  • PCI Express 4.0, adopted in 2017
  • PCI Express 5.0, adopted in 2019

The PCI bus has replaced the ISA bus and the short-lived VL bus found in older PCs. A PCI-ISA bridge, however, allows the ISA bus to be connected to the PCI bus. On systems of the Pentium generation and newer, this is the only way to connect ISA cards, since the ISA bus is the external system bus of the original PC. The PCI bus met the requirements for graphics, network and other interface cards for a long time.

However, after a while it was no longer fast enough for the graphics cards with 3D acceleration that were emerging at the time. In 1997 the Accelerated Graphics Port (AGP) was also established. This is based on the PCI bus, but is designed as a point-to-point connection with additional side channels and has meanwhile been further developed up to 8 times its original transmission rate. For almost all other plug-in card types, however, PCI has remained the standard to this day, but has been gradually replaced by PCI Express since 2005 (see below). Currently (as of 2019) PCI Express 4.0 is on the market, which is required by graphics cards such as the AMD Radeon RX 5700 XT in order to be able to use the bandwidth.

Unlike the ISA bus, PCI enables the dynamic configuration of a device without user intervention. During the boot process, the system BIOS analyzes the existing PCI devices and allocates the required resources. This allows the assignment of IRQs , port addresses and memory areas according to the local conditions. With ISA cards you often had to set the IRQ etc. to be used manually using a jumper . In addition, the PCI bus provides the operating system and other programs with a detailed description of all connected PCI devices through the PCI configuration space.

The PCI specification also regulates the physical layout of the bus (including the distance between the conductor tracks), electrical properties, timing and protocols. The devices or interfaces do not necessarily have to be accommodated on plug-in cards , but can also be located directly on the motherboard of the computer; the specification speaks here of planar devices .

General PCI bus specifications

Basic representation of the PCI architecture
Detection and configuration of PCI takes place via two IO registers
Bits Number
Bits 		Area description
32 bit port: 0CF8h
00 ... 1 02 00 ... 3 Selection of the transmission:
00 = Configuration PCI bridge
01 = Configuration PCI unit
02 ... 7 05 00 ... 31 Selection of the registration number
08 ... 10 03 00 ... 7 Selection of the PCI function (register group)
11 ... 15 05 00 ... 31 Address of the PCI unit, the PCI port;   not used for transmission 00  
16 ... 23 08th 00 ... 255 Bus number;   not used for transmission 00  
24 ... 31 08th 00 ... 255
32 bit port: 0CFCh
00 ... 31 32 00 ... 2 32 −1 Read / write the data of the selected register

The PCI bus is a synchronous bus with 33.33  MHz (= 30 ns per clock) or according to the 2.1 specification 66.66 MHz clock rate, i.e. 15  ns per clock. These values ​​are maximum values; according to the specification, the cycle can also be lower and also variable, for example to save power. Therefore the bus has a clock line. All signals are only transmitted with a rising clock edge ( single data rate ). The signals can be controlled via CMOS drivers, so the total power consumption is relatively low. The bus can be equipped with up to 10 devices, a distinction being made between master (controller of the transmission) and slave (may have to wait for data (or commands)). If necessary, a master can take control of the processes on the bus itself, which is particularly advantageous for cards with a high IO volume, such as network cards or hard disk controllers. Devices that are accommodated on the motherboard and that establish a connection to the host (PCI / host interface) or to a possibly existing ISA bus (PCI / ISA interface) also count as devices . For more than 10 PCI devices per system, additional PCI buses can be integrated into the system via PCI / PCI interfaces (PCI-PCI bridge). The data transfer runs in parallel.

A master always communicates with a slave on the PCI bus. Most PCI devices can be addressed both as slaves and as master transactions. A master is selected via an arbiter , which then has control over the bus. It starts a transfer by placing an address on the 32 data / address lines and a command on 4 command / byte lines. The data and addresses are transmitted over the same lines and separated from each other using time division multiplexing . An additional parity line allows errors to be recognized.

CPU and main memory are connected to the bus via a so-called host bridge. Most of the transactions on the bus take place between this bridge and the rest of the peripheral devices. In theory, peripheral devices can also communicate with one another, but this option is rarely used and is only supported as an option by most bridges. Since master-capable peripheral devices can address the host bridge as slaves, they are able to write directly to and read from the main memory - this corresponds to Direct Memory Access (DMA).

Each slave is assigned address ranges by the BIOS when the system is started. Cards can be clearly identified using manufacturer codes after booting. Data is then transmitted via the data lines, whereby the command / byte lines can be used to select the bytes in the 32-bit word. This enables 16 and 8 bit transfers in addition to 32 bit transfers.

In the most widespread PCI variant with 32 bit / 33 MHz, a maximum of 32 bits, i.e. H. 4 bytes are transferred so that the transfer rate is a maximum of 133 Mbytes / s (4 bytes in 30 ns). Both the master and the slave can signal via ready lines that they are ready to receive data. If the master or slave are not ready, no data will be transferred, the transfer will be stopped or slowed down.

Usually the master ends the data transfer. The slave can force an end of transmission via a STOP signal. Another master can request the bus via REQ, whereby the current transmission must be ended after a specified latency period and the new master can take over the bus.

The PCI bus requires a minimum of 47 (slave) or 49 (master) signals on the bus. From version 2.1 of the specification, a 64-bit extension has been defined that extends the data bus to 64 bits. 32-bit and 64-bit devices can coexist and communicate with each other in a system.

There are four interrupt lines on the bus so that each device can generate up to four different interrupts (INTA to INTD). The interrupt lines are not connected on the bus, but can be routed and assigned individually . Usually only INTA is used. However, depending on the slot, this can be assigned to a separate interrupt or, if there are not enough interrupts, it can be shared between different cards. The problems with the ISA bus, which could often not assign enough interrupts, are largely a thing of the past.

The PCI bus supplies the connected devices with voltage. The maximum permissible current intensity is specified for each supply voltage . Furthermore, the total output per slot is limited to 25 watts.

tension Current
(max)		 Power
(max)
0+3.3V ± 0.3V 6 A 20 W
0+5 V ± 05% 5 A 25 W
+12 V ± 05% 0.5 A 6 W
−12 V ± 10% 0.1 A 1.2 W
Sum of the total output 25 W
parameter PCI
2.0 		PCI 2.1 PCI
2.2 		PCI
2.3 		PCI
3.0 		PCI-X For comparison: AGP
32 bit 64 bit 1.0 2.0 1x 2x 4x 8x
Max. Bus width 32 bit 64 bit 64 bit 32 bit
Max. Clock (MHz) 033 066 100 133 266 533 066 133 266 533
Max. Data rate (MB / s) 133 266 533 800 1066 2133 4266 266 533 1066 2133
Slots per bridge 4th 2 2 1 1
tension 5 V 5 / 3.3V 3.3V 3.3V 3.3V 1.5V 0.8V
Introductory year 1993 1994 1999 2002 2004 1999 2003 1997 1999 2002

PCI bus signals

The type of inputs and outputs can be divided as follows:

Input in Normal entrance
output out Normal exit
Tri-state t / s bidirectional tri-state output
Sustained
tri-state		 s / t / s Low-active output that may only be driven by one device. If a device sets the line to low , it must set the line to high for at least one cycle in order to release the line again . Another device may use the line at the earliest after one cycle after the line has been released. A central pull-up resistor is necessary.
Open drain o / d Low active output, acts as an OR link with other devices. A central pull-up is necessary.
signal Art description
System signals:
CLK in Serves to synchronize all components. The clock frequency is 33 MHz or 66 MHz. The minimum frequency is 0 MHz.
RST # in Reset all system components.
Address and data signals:
AD [31..0] t / s multiplexed address and data signals
C / BE [3..0] # t / s multiplexed command and byte enable signals
PAR t / s Especially parity for data and address signals (AD [31..0] and C / BE [3..0]), which is transmitted delayed by one clock.
Control signals:
FRAME # s / t / s The master indicates that a transmission is in progress with FRAME #. If the transmission of the data is ended, the master takes back the line. A deactivated line means that the transmission has ended or has ended.
IRDY # s / t / s With Initiator Ready , the master indicates that a word can be transferred or accepted.
TRDY # s / t / s With Target Ready , the target indicates that a word can be transferred or accepted.
STOP# s / t / s The target indicates to the master that the transmission should be ended.
LOCK # s / t / s LOCK protects access to one or more targets during the transmission from the use of other masters.
IDSEL in Selection during the configuration phase
DEVSEL # s / t / s Target recognized address
Arbitration (master only):
REQ # s / t / s This indicates the intention of a master on the bus. This signal is a point-to-point connection from each master to a central arbiter.
GNT # in Allows access to the bus. This signal is a point-to-point connection from a central arbiter to each master.
Error signaling:
PERR # s / t / s One cycle after PAR , this signal indicates a data parity error (not with a special cycle command).
SERR # o / d System Error indicates a data or other system error with a special cycle command.
Interrupt signals:
INTA # o / d A device with a function indicates an interrupt. A device with more functions displays an interrupt A.
INTB # o / d A device with more than one function indicates an interrupt B.
INTC # o / d A device with more than one function displays an interrupt C.
INTD # o / d A device with more than one function displays an interrupt D.
Cache signals (optional, declared obsolete in PCI 2.x):
SBO # inout Snoop Backoff shows a "cache hit" for a modified cache line.
SDONE inout Snoop Done indicates the end of a snoop for the current access.
additional signals:
PRSNT1 #
PRSNT2 # 		out Shows the presence of a plug-in card and its energy consumption. At least one of the two signals (3 different combinations for 3 different consumption classes) is connected to ground on the card and the other possibly remains open. These signals are individually connected to a system chip for each slot and all have a pull-up. These signals are only available with plug-in cards, they do not exist with on-board peripherals, since on-board components cannot be exchanged and the power consumption is known in advance.
CLKRUN # o / d Controls the shutdown of the CLK signal for power saving purposes.
M66EN o / d This signal, which was originally a ground pin, signals the 66 MHz capability of a device by remaining unconnected or being wired as an input. Older or slower devices slow the entire bus down to 33 MHz by connecting the signal to ground.
64-bit extension signals:
D [63..32] t / s The upper 32 bits of the data signals.
C / BE [7..4] # t / s The upper 4 bits of the command and byte enable signals.
REQ64 # s / t / s Request64 indicates the intention of a master for a 64-bit transfer. This signal is a point-to-point connection from a central arbiter to each master.
GNT64 # in Grant64 allows access for a 64-bit transmission. This signal is a point-to-point connection from a central arbiter to each master.
PAR64 t / s Parity64 via AD [63..32] and C / BE [7..4] # offset by one clock.
JTAG signals:
TCK in Test clock
TDI in Test Data In
TDO out Test data out
TMS in Test Mode Select
TRST # in Test reset

Signals on the PCI bus - the # sign indicates that the signals are low active .

PCI ID

Each device or plug-in card on a PCI bus has a unique hardware identifier (ID). This is made up of three parts, which are used to identify the function (class ID), manufacturer and model (device ID).

     Class-ID : Hersteller-ID : Geräte-ID

Example:

     0200:8086:10B5

Here stands:

  • 0200 for an Ethernet network controller
  • 8086 for Intel Corporation (the number is hexadecimal, but the digits would stand for Intel's forefather of the x86 architecture in decimal notation)
  • 10B5 for the device 82546GB Gigabit Ethernet Controller (Copper)

The device is assigned to a specific group via the class ID. This makes it easier to identify unknown devices.

Operations on the PCI bus

After the configuration of all devices by the BIOS, all devices can be addressed via a command protocol. This is made up of the command, the address and a sequence of data.

C / BE description
3 # 2 # 1# 0 #
0 0 0 0 The interrupt acknowledge command is an implicit read access to the system interrupt controller . The "byte enable" bits indicate the size of the interrupt vector .
0 0 0 1 The special cycle command is for simple broadcast messages (?)
0 0 1 0 The I / O Read command is for reading from the memory, which is integrated as an I / O address space (English "address space").
0 0 1 1 The I / O write command for writing in the memory as an I / O address space is involved (English "address space").
0 1 0 0 reserved
0 1 0 1 reserved
0 1 1 0 The Memory Read command is for reading from the memory, which is integrated as "Memory Address Space".
0 1 1 1 The Memory Write command is for writing to the memory that is integrated as "Memory Address Space".
1 0 0 0 reserved
1 0 0 1 reserved
1 0 1 0 The Configuration Read command reads from the internal configuration registers (Configuration Space).
1 0 1 1 The Configuration Write command writes to the internal configuration register (configuration space).
1 1 0 0 The Memory Read Multiple instruction reads more than one cache line from memory.
1 1 0 1 The Dual Address Cycle command allows two 32-bit address lines to be sent one after the other in order to be able to address a 64-bit address range in a 32-bit PCI environment.
1 1 1 0 The Memory Read Line command reads a cache line from memory.
1 1 1 1 The Memory Write and Invalidate command writes at least one entire line of cache to memory.

On reserved commands must not react PCI devices.

Basic PCI variants

  • PCI Conventional, allows bus widths of either 32 or 64 bit and transfers with 33 or 66 MHz clock rate (133 to 533 MByte / s)
  • PCI-X, 64-bit version of PCI Conventional with 66, 100 or 133 MHz clock rate (533, 800 or 1067 MByte / s)
  • PCI-X 266 (PCI-X DDR / QDR), PCI-X with 266 MHz nominal clock (2133 to 4266 MByte / s)
  • Mini PCI , smaller design, only 32 bit, for notebooks etc.
  • PC Card or Cardbus , external cards (successor to PCMCIA), smaller design, 32 bit, for notebooks etc.
  • CompactPCI , electrically fully PCI-compatible, but in the form of slots with 3 or 6  U
  • PXI , further development of the CompactPCI optimized for measurement technology
  • PCI low profile, half height, 32 or 64 bit, see table
  • PC / 104-Plus, PCI-104 and PCI / 104-Express, fully PCI-compatible for batch computers, successor to PC / 104
  • ASUS Media Bus , proprietary solution for expanding the PCI slot by an ISA connection for combined graphics and sound cards, or combined SCSI controllers and sound cards
  • PCI Express (PCIe), is used as a standard socket for graphics and additional cards (such as RAID controllers).
  • ExpressCard , external cards (successor to the 32-bit PC card ), compatible with PCIe, smaller design, PCI Express 1x interface (1 lane), for notebooks etc.

Dimensions of the PCI variants

default Low profile
Card type inch mm Card type inch mm
Minimum height 0.945 ″ 024 mm
Maximum height 04.2 ″ 107 mm 2.536 ″ 064 mm
Maximum length short card 06.6 ″ 168 mm MD1 4.721 ″ 119.91 mm
long card 12.283 ″ 312 mm MD2 6.6 ″ 167.64 mm

Coding of the contact strip

Encodings for various 32-bit and 64-bit PCI cards
  • 3.3 V compatible cards have a notch on the left (towards the slot bracket)
  • 5V compatible cards have a notch on the right
  • Universal cards have both notches
  • Slots according to PCI 2.x have a web on the right (the side facing away from the slot bracket). The PCI 2.3 specification no longer supports 5 V cards, but these still physically fit into the slot. However, some mainboards still support 5 V cards in PCI 2.3 slots. But this is only possible with 33 MHz PCI clock. → Consult mainboard specification.
  • Slots according to PCI 3.0 have a web on the left (towards the slot bracket) so that only 3.3 V and universal cards with the corresponding notch can be inserted.

Other PCI variants

  • PXI is a bus based on PCI technology, which has been optimized for the special requirements in measurement and automation technology.
  • Extended PCI (PCI-X)
  • PCI Express (first called 3GIO [input / output of the third generation], abbreviation PCIe or PCI-E ) is, in contrast to the PCI bus, a serial point-to-point connection on the electrical level, which, however, supports PCI signaling and - Programming techniques are used and can therefore be treated by the operating system and software such as PCI. Since 2004, PCI Express has gradually replaced both PCI and AGP . It is not compatible with PCI or AGP.

Power management with PCI

The energy-saving functions for the PCI bus are part of an optional specification that is located between PCI versions 2.1 and 2.2. Every PM-capable device has an additional 8-byte-long field in the configuration space, which it can use to indicate which energy-saving modes it supports and can be controlled accordingly. Each PCI device can be in one of four possible operating modes (D0-D3). The higher the number, the less energy the device uses. Even if a device does not know anything about PCI power management, it supports modes D0 and D3, as these are equivalent to on and off . Whether and how much energy can be saved in the intermediate modes is at the discretion of the hardware manufacturer. A device can switch from a certain mode to all "lower" modes, as well as from any mode to the D0 state.

Although devices can be switched to a different energy-saving mode manually during operation, in most cases a global energy-saving mode is set for the computer with the help of APM or ACPI , which is controlled by the power management of the operating system. In modes D1 and D2, an appropriately equipped PCI device has the option of placing a so-called Power Management Event Signal (PME) on the bus at any time, which is then forwarded to the power management of the operating system and can be used for this purpose to "wake up" the system again globally on request, for example when a network card detects incoming data that must be processed.

Terms

  • Fast back-to-back: If all devices support this mode, the idle phase between two PCI cycles can be omitted. This increases the data throughput on the bus.
  • Special Cycle: “Special Cycle” can be used to send broadcast messages to all connected devices.
  • Address space: one of three address areas - memory, I / O or configuration space
  • Configuration Space: The "Configuration Space" is a memory area (256 or 4096 bytes for PCI-X and PCIe) of each PCI device, which is used to identify and configure the device. The configuration space consists of a standardized header and additional device-specific data such as address areas. The BIOS or the driver for a PCI device can use this data to configure the device appropriately.

Interest Groups

Special Interest Group

In 1992 the special interest group "PCI-SIG" (original name: "Peripheral Component Interconnect Special Interest Group") was founded. The task of the PCI-SIG is the administration and further development of the PCI standard. Companies and organizations can become members of PCI-SIG. In 2007 there were more than 800 members.

PCI Industrial Computer Manufacturers Group

The PCI Industrial Computer Manufacturers Group ( PICMG ), founded in 1994, is a consortium of over 450 companies that want to expand the PCI standard for use in the industrial sector, in medicine, the military and telecommunications. This resulted in specifications such as CompactPCI or AdvancedTCA .

literature

  • Don Anderson, Tom Shanley: PCI System Architecture. 4th edition. Addison-Wesley, Reading MA et al. 1999, ISBN 0-201-30974-2 .

Web links

Commons : PCI  - collection of pictures, videos and audio files

Individual evidence

  1. ↑ Hardware and PCI Overview FAQs . sun.com, December 4, 2008