Motorola 68060
The Motorola 68060 is a 32-bit - processor from Motorola (later Freescale , now NXP ). It was published in 1994 as the successor to the Motorola 68040 and is the most powerful processor in the Motorola 68000 family .
architecture
The Motorola 68060 (mostly simply called 060 , i.e. zero-sixty ) is not a simple redesign of the 68040, but has been completely redeveloped based on the experience with the 68040. A second unit for integer calculations has been added ( superscalarity ) and an extension for integer multiplications that only requires two bars per multiplication. The unit for floating point calculations ( FPU ) has been replaced by a faster variant, but some more complex functions of the 68881/68882 have not been implemented. Even compared to the FPU of the 68040Some functions have been deleted, but this contributes enormously to the overall execution speed of the 68060-FPU (about a factor of 3.5). The missing functionality must be emulated by a software library provided by the manufacturer. Furthermore, a logic for branch prediction was added. The 68060 has about two to three times the computing power of a 68040 with the same clock rate. The development team for the 68060 was led by Joe Circello.
The 68060 has an architecture similar to the Intel Pentium . Some of the internal logic (some function blocks) does not work with twice the bus speed, but with the triple bus speed compared to the 68040 . However, this cannot be compared with the doubling and tripling of the clock rate of the DX processors in the PC area. Both processors have two superscalar in-order pipelines. Each pipeline has an instruction decoder. This breaks down complex machine instructions into simpler ones before they are processed. Internal processing takes place in four stages according to the RISC principle. The real difference to the Pentium is the non-superscalar floating point unit ( FPU ) of the 68060. Either two integer instructions and one branch instruction or one integer, one floating point and one branch instruction can be processed in parallel. However, not all instructions can be processed independently of one another, resulting in an average IPC of around 1.3. The 68060 therefore only achieves about a third of the speed of a Pentium in the floating point range with the same clock rate. In contrast to this, the integer multiplication and bit shifting operations are much faster. In addition, the 68060 can execute simple commands in the addressing unit, so that the results of the addressing logic are available two computing cycles before those of the ( ALU ). This type of processing leads to the zero-cycle branch behavior, which means that a branch usually does not cost any computation cycles. A large amount of compiled commercial code was analyzed for these optimizations. In addition, the 68060 has two MMUs in accordance with the Harvard architecture , one for data paging and one for instruction paging . In the integer area, it is largely binary compatible with its predecessors. Part of the complex addressing modes of the 68020 / 68030 are not supported. Compatibility in the FPU area is only guaranteed by using the emulation library. The functionality of the MMU has been reduced in comparison to the 68030 and 68040 , for example only page sizes of 4 KiB and 8 KiB are supported.
The 68060 is the first and only member of the 68000 family with energy-saving functions . The CPU can dynamically clock down or clock up different logic blocks or deactivate them completely depending on the workload. These functions can be accessed via software.
The 68060 was the last development in the Motorola 68000 family . Motorola stopped the further development in favor of the PowerPC processors. The 68060 was last used in some late Amiga models and their accelerator card expansions. There were also some Atari ST descendants that made use of the last generation. The TOS-compatible Medusa Hades with 68060 processor and the CT60 and CT63 expansion cards for the Atari Falcon were included. Apple and a large part of the Unix world switched to RISC -based processors after the 68040 . The 68060 was launched at 50 MHz (based on Motorola's 0.6 µm manufacturing process). Later models experienced a reduction in the structure width to 0.42 µm and could thus be operated with 66 MHz, sometimes even with 75 MHz. Some of the EC and LC variants were even operated at 80 MHz or even 90 MHz. The 0.42 µm processors were very rare as Motorola was now concentrating on its PowerPC processors.
variants
- 68060 - full CPU with FPU and MMU
- 68LC060 - deactivated FPU, MMU present
- 68EC060 - FPU and MMU deactivated
technical features
| Working frequencies | 50 MHz, 60 MHz, 66 MHz, 75 MHz |
| Operating voltage |
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| Working temperature | −40 ° C to 70 ° C (85 ° C with more recent masks) |
| Manufacturing process | static CMOS 0.6 μm and later 0.42 μm |
| Construction | PGA 206 (compatible with 68040 ), TBGA 304 (31 × 31 × 1.7 mm³; 1.27 mm pitch ) |
| Data bus | 32 bit |
| Address bus | 32 bit |
| Instruction set | CISC (internally similar to the RISC working method by breaking down macro-ops into micro-ops) |
| Cache |
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| register |
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| Transistors | ≈2,500,000 |
| performance |
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Trivia
- LC and EC are variants of the CPU where on the during the manufacturing process , the errors within the FPU and / or MMU unit were identified. In order to increase the production yield, the affected units were specifically deactivated and the CPU with a correspondingly reduced range of functions was sold more cheaply.
- The Viper 1260 (an Amiga 1200 - Turbo Card ) used a 50 MHz 68060 with over-clocked at 56 MHz.
- The Apollo 1260 (an Amiga 1200 accelerator card) can be clocked with a 68060 Rev.6 up to 80 MHz.
- The CT60 (an Atari Falcon expansion card) achieves clock rates of 90 MHz to over 100 MHz with processors of Rev.6.
