Agnus (Amiga)
The Agnus (lat. For lamb ) is one of the custom chips in the chipset of the Commodore Amiga . In the later versions it was renamed Alice .
Surname
"Agnus" is an acronym of "Address Generator" ( English A dress G e n erator U nit s ).
properties
The module is responsible for the control of the so-called chip RAM in the Amiga, provides the video sync signals (HSY, CSY, VSY) and contains the coprocessors Copper and Blitter . Agnus also contains the complete DMA logic for all 6 possible sources. A screen line serves as a time reference for the timing of the individual DMA accesses. In each line, Agnus distributes 225 memory accesses to the DMA channels and the CPU . A row and a column counter are responsible for correct timing (HSY, VSY). The timing can also be controlled externally via these signals ( genlock ). An essential main component of Agnus is the large address generator. All custom chips of the Amiga can directly access the RAM independent of the CPU . To do this, however, these chips require a free DMA channel and the address generator. Access to the RAM is carried out via the DMA channels. The address generator converts the signals from a chip into complete memory addresses. Agnus can copy data independently of the main processor in memory or from a peripheral device to a memory area or vice versa.
None of the other chips in the Amiga chipset have DMA channels or address generators. All memory accesses therefore run centrally via Agnus and are controlled and coordinated by him. Agnus has a total of 25 DMA channels via which 25 different devices can write data to or read from the memory without the aid of the CPU. This video data fetched from the chip RAM by Agnus and displayed by Denise includes, in addition to the pixel data, palette and sprite data as well as the copper lists. The data from BOBs are also fetched from Agnus via DMA, but then copied directly to the position to be displayed within the video memory in the chip RAM with the blitter integrated in Agnus.
On the one hand, Agnus fetches the video and sound data from the chip RAM and, on the other hand , can also copy data within the chip RAM and process it ( blitting ), but can also generate data, namely when drawing lines and filling areas with the blitter .
The original version of the Agnus can address 512 KiB chip RAM ( OCS ). It was manufactured in a DIP housing and only used in the Amiga 1000 and Amiga 2000 with A-Board . The successor models Amiga 500 and Amiga 2000 with B-Board already have a PLCC socket for the so-called Fat Agnus due to this housing shape (see below under PLCC versions ). The Fat Agnus appeared in different versions for different chip RAM sizes with different functions (OCS / ECS ). For the ECS versions of the Fat Agnus, expressions not coined by the manufacturer and therefore used inconsistently, such as Big Agnus , Super Agnus or a combination of these, are also circulating .
The Alice chip is the further development of Fat Agnus for the AGA (AA) chipset . Alice was redeveloped based on the A3000-Agnus and specially tailored to the newer CPUs (from MC68020). Because the bus is 32 bits wide with these processors, some signals could be combined or removed. This meant that 2 MiB of chip RAM could be used. Alice cannot be built into old Amigas, however. It was developed only for Amigas with AGA (AA) chipset and is used in the Amiga 1200 , Amiga 4000 models and in the CD³² .
Versions
- 8361 (A1000, A2000A, OCS, DIP housing, NTSC )
- 8367 (A1000, A2000A, OCS, DIP housing, PAL )
- 8370 (A500, A2000, OCS, PLCC housing, NTSC)
- 8371 (A500, A2000, OCS, PLCC housing, PAL)
- 8372 (A500, A2000, ECS, 1 MiB Chip-RAM)
- 8372-A (A500, A2000, ECS, 1 MiB Chip-RAM)
- 8372-B (A500 +, A600, ECS, 2 MiB Chip-RAM)
- 8372-AB (A3000 (T), ECS, 2 MiB Chip-RAM)
- 8374 Alice (A1200, A4000 (T), CD³², AGA)
- 8375 (A500 +, A600, ECS, 2 MiB Chip-RAM)
The Fat- (PLCC) -Agnus 8370-72 / 75 exists in different versions:
- 1 MiB RAM, but only 512 KiB can be used as Chip-RAM (OCS) due to non-expanded registers, the 2nd half is mapped as pseudo Fast-RAM to $ C00000 ('Ranger-Memory')
- 1 MiB RAM, fully usable as chip RAM (ECS)
- 2 MiB RAM, fully usable as chip RAM (ECS in A3000 (T), A500 +, A600)
ECS chips can be switched between PAL and NTSC; there are dedicated versions in the OCS.
DMA channels
priority | Surname | number | Cycles / raster line | chip | comment |
---|---|---|---|---|---|
MPU | 1 | varies | CPU | ||
A. | Blitter | 4th | varies | Agnus (internal) | sends cycles to the CPU, unless BLTPRI is activated |
B. | Bitplane | 6th | 80 | Denise | with extreme overscan sprite channels are impaired |
C. | Copper | 1 | varies | Agnus (internal) | |
D. | Audio | 4th | 4th | Paula | |
E. | Sprites | 8th | 16 | Denise | |
F. | Disk | 1 | 3 | Paula | |
G | Memory refresh | 1 | 4th | - | |
Source: Amiga 500 plus Service Manual |
Pin assignment
DIP version
OCS | |
A1000 / 2000 | |
8361/67 | |
1 | D8 |
2 | D7 |
3 | D6 |
4th | D5 |
5 | D4 |
6th | D3 |
7th | D2 |
8th | D1 |
9 | D0 |
10 | Vcc (+ 5V) |
11 | _RES |
12 | _INT3 |
13 | DMAL |
14th | _BLS |
15th | _DBR |
16 | _ARW |
17th | _RGA8 |
18th | _RGA7 |
19th | _RGA6 |
20th | _RGA5 |
21st | _RGA4 |
22nd | _RGA3 |
23 | _RGA2 |
24 | _RGA1 |
25th | CCK |
26th | CCKQ |
27 | VSS |
28 | DRA0 |
29 | DRA1 |
30th | DRA2 |
31 | DRA3 |
32 | DRA4 |
33 | DRA5 |
34 | DRA6 |
35 | DRA7 |
36 | DRA8 |
37 | _FIR0 |
38 | _VSY |
39 | _CSY |
40 | _HSY |
41 | VSS |
42 | D15 |
43 | D14 |
44 | D13 |
45 | D12 |
46 | D11 |
47 | D10 |
48 | D9 |
Source: A2000A wiring diagram |
PLCC versions
The pin assignment is interesting for exchange / modification. The type specifications are intended for reference only; It is not possible to directly deduce the pin assignment of an existing Agnus chip , as this was apparently only determined during the packaging, regardless of the chip .
OCS / ECS | ECS | ECS | AGA | |
A500 / 2000 | A3000 | A500 + / 600 | A1200 / 4000 | |
8370/71 | 8372 | 8375 | 8374 Alice | |
1 | RD13 | DRD13 | DRD13 | DRD13 |
2 | RD12 | DRD12 | DRD12 | DRD12 |
3 | RD11 | DRD11 | DRD11 | DRD11 |
4th | RD10 | DRD10 | DRD10 | DRD10 |
5 | RD9 | DRD9 | DRD9 | DRD9 |
6th | RD8 | DRD8 | DRD8 | DRD8 |
7th | RD7 | DRD7 | DRD7 | DRD7 |
8th | RD6 | DRD6 | DRD6 | DRD6 |
9 | RD5 | DRD5 | DRD5 | DRD5 |
10 | RD4 | DRD4 | DRD4 | DRD4 |
11 | RD3 | DRD3 | DRD3 | DRD3 |
12 | RD2 | DRD2 | DRD2 | DRD2 |
13 | RD1 | DRD1 | DRD1 | DRD1 |
14th | RD0 | DRD0 | DRD0 | DRD0 |
15th | Vcc | Vcc | Vcc | Vcc1 |
16 | RST * | _RESET | _RESET | / RESET |
17th | INT3 | _INTR | _INTR | / INTR |
18th | DMAL | DMAL | DMAL | DMAL |
19th | BLS * | _BLISS | _BLISS | / BLS |
20th | DBR * | _BLIT | _BLIT | / DBR |
21st | RRW | _WE | _WE | / WE |
22nd | PRW | R / W | R / W | R / W |
23 | RGEN * | _RAIN | _RAIN | _RAIN |
24 | AS * | _AS | _AS | NC2 |
25th | RAMEN * | _RAMEN | _RAMEN | / RAMEN |
26th | RGA8 | RGA8 | RGA8 | RGA8 |
27 | RGA7 | RGA7 | RGA7 | RGA7 |
28 | RGA6 | RGA6 | RGA6 | RGA6 |
29 | RGA5 | RGA5 | RGA5 | RGA5 |
30th | RGA4 | RGA4 | RGA4 | RGA4 |
31 | RGA3 | RGA3 | RGA3 | RGA3 |
32 | RGA2 | RGA2 | RGA2 | RGA2 |
33 | RGA1 | RGA1 | RGA1 | RGA1 |
34 | 28MHz | 28MHz | 28MHz | SCLK |
35 | XCLK | A20 | A20 | A20 |
36 | XCLKEN * | _XCLKEN | _CDAC | 14MHz |
37 | CDAC * | _CDAC | 7MHz | / CDAC |
38 | 7MHz | 7MHz | CCKQ | 7MHz |
39 | CCKQ | CCKQ | CCK | CCKQ |
40 | CCK | CCK | 14M | CCK |
41 | TEST | TEST | GND | / NTSC |
42 | Vss | Vss1 | DRA0 | GND2 |
43 | MA0 | DRA0 | DRA1 | DRA0 |
44 | MA1 | DRA1 | DRA2 | DRA1 |
45 | MA2 | DRA2 | DRA3 | DRA2 |
46 | MA3 | DRA3 | DRA4 | DRA3 |
47 | MA4 | DRA4 | DRA5 | DRA4 |
48 | MA5 | DRA5 | DRA6 | DRA5 |
49 | MA6 | DRA6 | DRA7 | DRA6 |
50 | MA7 | DRA7 | DRA8 | DRA7 |
51 | MA8 | DRA8 | _LDS | DRA8 |
52 | LDS * | _LDS | _UDS | Vcc2 |
53 | UDS * | _UDS | _CASL | NC1 |
54 | CASL * | _CASL | _CASU | / CAS |
55 | CASU * | _CASU | DRA9 | Vbb |
56 | RAS1 * | DRA9 | _RAS1 | DRA9 |
57 | RAS0 * | _RAS | _RAS0 | / RAS |
58 | Vss | Vss2 | GND | GND3 |
59 | A19 | A19 | A19 | A19 |
60 | A1 | A1 | A1 | A1 |
61 | A2 | A2 | A2 | A2 |
62 | A3 | A3 | A3 | A3 |
63 | A4 | A4 | A4 | A4 |
64 | A5 | A5 | A5 | A5 |
65 | A6 | A6 | A6 | A6 |
66 | A7 | A7 | A7 | A7 |
67 | A8 | A8 | A8 | A8 |
68 | A9 | A9 | A9 | A9 |
69 | A10 | A10 | A10 | A10 |
70 | A11 | A11 | A11 | A11 |
71 | A12 | A12 | A12 | A12 |
72 | A13 | A13 | A13 | A13 |
73 | A14 | A14 | A14 | A14 |
74 | A15 | A15 | A15 | A15 |
75 | A16 | A16 | A16 | A16 |
76 | A17 | A17 | A17 | A17 |
77 | A18 | A18 | A18 | A18 |
78 | LP * | _LPEN | _LPEN | / LPEN |
79 | VSY * | _VSYNC | _VSYNC | / VSYNC |
80 | CSY * | _CSYNC | _CSYNC | / CSYNC |
81 | HSY * | _HSYNC | _HSYNC | / HSYNC |
82 | Vss | Vss3 | GND | GND1 |
83 | RD15 | DRD15 | DRD15 | DRD15 |
84 | RD14 | DRD14 | DRD14 | DRD14 |
Sources: A500 Service Training, A3000 Service Manual, A500 + Service Manual, A1200 circuit diagram |
See also
Individual evidence
- ↑ Commodore SCHEMATIC AMIGA 2000 380710 REV 6
- ↑ "Difference of 8372A vs 8375"