Circuit underutilization: Difference between revisions
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{{Short description|Not using the area or components of an integrated circuit to full efficiency}} |
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{{Use dmy dates|date=May 2019|cs1-dates=y}} |
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{{Use American English|date=March 2019}} |
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'''Circuit underutilization''' also '''programmable circuit underutilization''', '''gate underutilization''', '''logic block underutilization''' refers to a physical incomplete utility of [[Crystalline silicon|semiconductor grade silicon]] on a |
'''Circuit underutilization''' also '''chip underutilization''', '''programmable circuit underutilization''', '''gate underutilization''', '''logic block underutilization''' refers to a physical incomplete utility of [[Crystalline silicon|semiconductor grade silicon]] on a standardized mass-produced [[Programmable logic device|circuit programmable]] chip, such as a [[gate array]] type [[Application-specific integrated circuit|ASIC]], an [[Field-programmable gate array|FPGA]], or a [[Complex programmable logic device|CPLD]]. |
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==Gate array== |
==Gate array== |
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In the example of a [[gate array]], which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.<ref name="chipdes">http://chipdesignmag.com/display.php?articleId=386</ref> |
In the example of a [[gate array]], which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.<ref name="chipdes">{{Cite web|url=http://chipdesignmag.com/display.php?articleId=386|title=Chip Design » The Death of the Structured ASIC by Bob Zeidman, president, Zeidman Technologies|website=chipdesignmag.com|language=en|access-date=2018-10-07}}</ref> |
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==FPGA== |
==FPGA== |
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Due to the design components of |
Due to the design components of field-programmable gate array into [[logic block]]s, simple designs that underutilize a single block suffer from gate underutilization, as do designs that overflow onto multiple blocks, such as designs that use wide gates.<ref>{{cite book |citeseerx=10.1.1.52.3689 |title=Designing for High Speed-Performance in CPLDs and FPGAs |first1=Zeljko |last1=Zilic |first2=Guy |last2=Lemieux |first3=Kelvin |last3=Loveless |first4=Stephen |last4=Brown |first5=Zvonko |last5=Vranesic |date=June 1995 |work=Proceeding of the Third Canadian Workshop on FPGAs }}</ref> Additionally, the very generic [[Field-programmable gate array#Architecture|architecture of FPGAs]] lends to high inefficiency; [[multiplexer]]s occupy silicon real estate for programmable selection, and an abundance of [[flip-flop (electronics)|flip-flops]] to reduce [[Flip-flop (electronics)#Setup.2C hold.2C recovery.2C removal times|setup and hold]] times, even if the design does not require them,<ref name="chipdes"/> resulting in 40 times less density than of [[standard cell]] [[ASIC]]s. |
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in CPLDs and FPGAsZeljko Zilic, Guy Lemieux, Kelvin Loveless, Stephen Brown, and Zvonko Vranesic Department of Electrical and Computer Engineering, |
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University of Toronto, Canada</ref> Additionally, the very generic architecture of FPGAs lends to high inefficiency; [[multiplexer]]s occupy silicon real estate for programmable selection, and an abundance of [[flip-flop (electronics)|flip-flops]] to reduce [[Flip-flop (electronics)#Setup.2C hold.2C recovery.2C removal times|setup and hold]] times, even if the design does not require them.,<ref name="chipdes"/> resulting in 40 times less density than of [[standard cell]][[ASIC]]s. |
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==See also== |
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* [[Circuit minimization]] |
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* [[Don't-care condition]] |
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==References== |
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{{reflist}} |
{{reflist}} |
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{{Programmable Logic}} |
{{Programmable Logic}} |
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[[Category:Gate arrays| |
[[Category:Gate arrays|*]] |
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Latest revision as of 01:10, 17 December 2023
Circuit underutilization also chip underutilization, programmable circuit underutilization, gate underutilization, logic block underutilization refers to a physical incomplete utility of semiconductor grade silicon on a standardized mass-produced circuit programmable chip, such as a gate array type ASIC, an FPGA, or a CPLD.
Gate array[edit]
In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.[1]
FPGA[edit]
Due to the design components of field-programmable gate array into logic blocks, simple designs that underutilize a single block suffer from gate underutilization, as do designs that overflow onto multiple blocks, such as designs that use wide gates.[2] Additionally, the very generic architecture of FPGAs lends to high inefficiency; multiplexers occupy silicon real estate for programmable selection, and an abundance of flip-flops to reduce setup and hold times, even if the design does not require them,[1] resulting in 40 times less density than of standard cell ASICs.
See also[edit]
References[edit]
- ^ a b "Chip Design » The Death of the Structured ASIC by Bob Zeidman, president, Zeidman Technologies". chipdesignmag.com. Retrieved 2018-10-07.
- ^ Zilic, Zeljko; Lemieux, Guy; Loveless, Kelvin; Brown, Stephen; Vranesic, Zvonko (June 1995). Designing for High Speed-Performance in CPLDs and FPGAs. CiteSeerX 10.1.1.52.3689.
{{cite book}}:|work=ignored (help)
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