Circuit underutilization
Circuit underutilization also Programmable circuit underutilization, gate underutilization, logic block underutilization refers to the incomplete utility of semiconductor grade silicon on a standarized mass produced circuit programmable chip, such as a gate array type ASIC, FPGA, or CPLD.
Gate array
In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.[1]
FPGA
Due to the design components of FPGA into logic blocks, simple designs that underutilize a single block suffer from gate underutilization.[2] Additionally, the very generic architecture of FPGAs lends to high inefficiency; multiplexers occupy silicon real estate for programmable selection, and an abundance of flip-flops to reduce setup and hold times, even if the design does not require them.[1], resulting in 40 times less density than of standard cellASICs.
CPLD
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CPLD like FPGA, also suffer from similar issues.
References
- ^ a b http://chipdesignmag.com/display.php?articleId=386
- ^ http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.52.3689&rep=rep1&type=pdf Designing for High Speed-Performance in CPLDs and FPGAsZeljko Zilic, Guy Lemieux, Kelvin Loveless, Stephen Brown, and Zvonko Vranesic Department of Electrical and Computer Engineering, University of Toronto, Canada