Lift-off procedure

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The lift-off process ( English lift-off technique ) is a process sequence in semiconductor and microsystem technology for the production of a mostly metallic microstructure. In a first process step, structured thin layers are produced on the surface of substrates such as wafers . The target material is then deposited over the entire surface of this structured sacrificial layer . Those areas in which the target material is located on the sacrificial layer are then removed in a further process step, and the remaining structures form the desired microstructure. The size of the structures that can be produced using the lift-off process ranges from a few tens of nanometers to centimeters , with typical structure sizes in the micrometer range. The process is used, among other things, for the production of conductor track levels or contact surfaces in the production of integrated circuits (ICs) and microsystems . In contrast to this additive or structural process, there are the subtractive processes, in which a homogeneous layer of the target material is first deposited over the entire surface of the substrate and the later structure is created by etching this layer.

process description

Schematic representation of an example process sequence

The lift-off process is a relatively simple and efficient sequence of various basic processes in semiconductor technology. A typical process sequence consists for example of the photolithographic structuring , the layer deposition and the removal of the photoresist layer. In the course of time, however, different variants have developed, the possibilities of which depend very much on the process conditions and settings used. Therefore, only the basic process steps are described below.

The lift-off process begins with the entire surface deposition of the later sacrificial layer (often photoresist ) on a pretreated substrate. The pretreatment usually includes cleaning the substrate and, if necessary, planarizing the surface (for example by chemical-mechanical polishing or the application of an adhesion promoter layer ). The photolithographic structuring of the sacrificial layer then takes place with an inverse pattern of the later structure. The parameters of the structure of the sacrificial layer should be set in such a way that highly vertical side walls or side walls with a slight undercut (negative side wall angle) result.

After the structuring of the sacrificial layer, the entire surface of the target material, for example aluminum , is deposited by thermal evaporation . There should be no connection between the deposited target material on the substrate and the target material on the sacrificial layer, so that on the one hand this connection does not have to be separated later, on the other hand the side surfaces of the sacrificial layer are still uncovered and thus the removal of the sacrificial layer in the last Process step is not hindered. A connection between the two areas can be avoided through two framework conditions:

  1. The layer thickness of the sacrificial material should be at least three times that of the target material, otherwise the sacrificial layer structure will be too filled and block later process steps.
  2. The coating process should have poor edge or side wall coverage, so that as little material as possible is deposited on the side wall of the sacrificial layer. Thermal evaporation or certain variants of sputter deposition are suitable for this, for example .

When depositing the target material, it must also be ensured that the sacrificial layer survives this work step undamaged. For the use of photoresist as a sacrificial layer, this means that the process temperature must not exceed the glass temperature of the photoresist. For this reason, the target layer is usually deposited at room temperature and is therefore often amorphous or polycrystalline .

In the last process step, the sacrificial layer is removed using a wet chemical process. For this purpose, for example, the photoresist can be dissolved in a solvent (e.g. acetone ), if necessary with the aid of ultrasound . The sacrificial layer is dissolved from the side walls (flanks). The target material on top of the sacrificial layer is lifted off with ( English lift off ) and washed away. After that, the target material only remains in regions where it had direct contact with the substrate.

Typical process errors

Schematic representation of typical errors

After the sacrificial layer has dissolved, the finished structure can have three typical process-related defects:

  1. Remaining material : This is usually undissolved sacrificial layer material and the target material on it. This problem occurs when the sacrificial material was surrounded by target material and was therefore difficult or impossible to attack by the solvent.
  2. Redeposition : This is understood to mean the accumulation of detached material, which is deposited again on the surface. These particles are difficult or impossible to remove after the process, especially after the wafer has dried.
  3. Burrs : This is target material that was deposited on the sidewalls of the sacrificial layer and remains after the sacrificial layer is removed. Such burrs have negative effects on subsequent manufacturing steps, because on the one hand they create an undesirable topography on the wafer , which, for example, hinders the uniform deposition of a further layer. On the other hand, they can also "fall over" and thus create an electrical short circuit .

The three defect patterns are more or less the result of a side wall covering of the structured sacrificial layer by target material. It follows from this that a good structure quality depends crucially on the profile of the sacrificial layer and the "edge coverage" of the coating process. A combination of undercut (negative) flanks or sacrificial layer systems, in which the bottom layer has been etched back, and a coating process with poor edge coverage are favorable here.

Process variants

Process variants with different sacrificial layers after a deposition of the target material (black areas). The following are shown schematically:
A) a single-layer system with a negative flank angle, e.g. B. photoresist with image reversal step
B) a two-layer system in which the lower layer was etched back after structuring.

The lift-off principle for the production of metal structures was already described in the 1940s, before the beginnings of microelectronics. Since then, numerous variants have been developed in the literature that differ from one another with regard to the deposited layer, the sacrificial layer and the chemistry used, as well as numerous process parameters and the areas of application. As already mentioned, simple processes use a layer of photoresist or a polymer such as polymethyl methacrylate (PMMA), whereby this sacrificial layer can be structured using conventional photolithography - first introduced in 1969 by Hatzakis for the production of conductor tracks and source / drain contacts made of aluminum. Process variants that use electron beam or imprint lithography have also been described. Further developed variants use more or less complex layer stacks as a sacrificial layer, for example photoresist / aluminum / photoresist, polyimide / molybdenum or polyimide / polysulfone / silicon dioxide stacks etc. The use of an additional etching step with which the side edge of the lowest sacrificial layer is etched back, acts like an undercut edge profile and prevents the formation of a closed layer on the side walls.

In addition to process variants with different sacrificial layers or layer systems, processes were also described in which the lift-off effect does not occur through chemical dissolution, but rather by lifting the coated sacrificial layer with the help of an adhesive tape ( tape-assisted lift off ) or through stresses introduced in the material (cf. carbon dioxide snow technology ).

Some process variants are described below as examples.

Photolithography with image reversal step

Process steps for the production of a photoresist sacrificial layer with an undercut profile using a reverse heating step and a special positive photoresist (direct process)

When using a photoresist sacrificial layer, what is known as an image reversal process is often used, with the help of which an undercut edge profile can be generated. This is only possible with difficulty with a simple photolithographic structuring, since light is always more strongly absorbed in the upper areas of the lacquer layer and a profile with steep flanks or overcut results after development, cf. Step 2. in the adjacent figure. Reversal photoresists (Engl. Image-reversal resists ) offer the possibility of erecting (Engl. Image reversal ) of the mask. Depending on the reversal photoresist used, a distinction is made between a direct (acid-catalytic) and an indirect (basic) reversal process; depending on the process, they result in a negative or a positive image of the mask.

In acidic - catalytic reverse photoresists, for example a Diazonaphtoquinon (DNQ) / novolak -Fotolack in combination with an admixed säureaktivierbaren polymerizer (. Eg hexamethoxymethylmelamine , HMMM), the process control corresponds to the exposure largely a normal photolithographic patterning (paint application, soft bake etc .). A development of the photoresist (positive resist) immediately after this exposure would therefore result in a positive image of the mask structure. However, an additional reversal process before development reverses the solubility ratios. That is, after exposure, insoluble areas become soluble and vice versa. This is essentially achieved through two sub-steps. First of all, the exposure is followed by a so-called image reversal bake . The effect of temperature causes cross-linking reactions in the exposed areas of the photoresist and after a resting phase in which sufficient rehydration is ensured (longer storage in air is sufficient), the second additional step follows. A flood exposure of the entire wafer causes the formation of 3-indenecarboxylic acid in the areas not yet exposed and makes these areas soluble in relation to the alkaline developer . After development, a negative image of the mask structure is created with an undercut flank profile.

In the case of basic reversal photoresists, the photoresist layer is first exposed to an amine vapor or an ammonia solution after exposure . A basic catalyst diffuses into the layer, which leads to the decomposition of the 3-indenecarboxylic acid formed in the exposed areas during the subsequent reverse heating. The thus created Inden - derivatives are very effective Löslichkeitshemmer. As in the direct process, before the lacquer is developed, a flood exposure takes place, during which the initially unexposed areas are exposed and thus become soluble.

In both process variants, the flank angle of the photoresist profile can be influenced during the first exposure by varying the exposure time. As already mentioned, this happens due to the depth-dependent absorption behavior of the light and the resulting degree of crosslinking after reverse heating. A high exposure dose leads to steep flanks and a low exposure dose leads to strongly undercut flanks. With such a profile, the risk of undefined tear-off edges on the side walls can be avoided during the lift-off process. In addition, the resulting sacrificial layer has increased thermal stability up to 200 ° C.

Electron beam lithography

Another possibility of producing an undercut photoresist profile is structuring the sacrificial layer using electron beam lithography . In this process variant, the scattering behavior of electrons or their energy distribution in the photoresist layer is used. Depending on the output energy, there is a more or less elongated, pear-shaped energy distribution. The upper area of ​​this distribution can be used to produce an undercut profile. Here the distribution cross-section also increases with increasing depth. In order to achieve this profile in a sacrificial layer only a few hundred nanometers thick, however, relatively low energies are necessary, which in turn has a negative effect on the resolution. This is especially true with dense structures. For the production of dense structures with line widths in the range below 100 nm, high energies are therefore still used, even if this makes it more difficult to achieve the necessary profile undercut.

The use of a double-layer photoresist system can help. The lower layer has a significantly higher sensitivity (e.g. 50 times higher) than the upper layer, and profile undercut can be achieved even with high radiation energy. Frequently used material combination for such a system is a layer stack made of a top layer made of polymethyl methacrylate (PMMA; with high molar mass and lower electron sensitivity) and an underlying layer made of one of its copolymers (e.g. P (MMA-MAA) with low molar mass and higher electron sensitivity). The advantage of such a material combination is that both layers can be developed with the same solution.

Carbon dioxide snow technology

A newer lift-off variant uses frozen carbon dioxide particles ( carbon dioxide snow ) to remove a metal layer (target material) on the photoresist sacrificial layer. Solid carbon dioxide forms at temperatures below −60 ° C and thus well below the typical process temperatures for coating. When the metal and photoresist layers cool, the different thermal expansion coefficients cause mechanical stresses at the interface between the two materials, which lead to breakage or detachment of the metal film. The detached metal is then removed by a carbon dioxide jet at speeds of up to 40 m / s. Usually, the back of the substrate is heated to up to +60 ° C, which further increases the mechanical tension at the interfaces and at the same time reduces the mechanical tension between the desired metal structures on the substrate. After the metal layer has been detached from the sacrificial layer, it can easily be removed by wet-chemical or plasma ashing . The advantage of this method is that the metallic particles are removed immediately and the sample surface is thus better protected against repeated deposition.

application

The lift-off process is a very general production method with which in principle all metals and their alloys as well as multiple layers can be structured. Since, unlike subtractive structuring by etching, no etching processes or etching chemistry tailored to the materials to be etched are required, approximately the same lift-off process can always be used. A similar deposition of the target material only needs to be guaranteed.

The procedure offers advantages in the following cases, for example:

  1. In cases in which direct etching with a sufficiently high selectivity for the materials already deposited is not available.
  2. In the case of multiple layers, in which the individual layers are first applied one after the other and then structured together.
  3. For materials such as aluminum- copper alloys, which form residues that are difficult to remove when they are structured by dry etching .

Furthermore, the inclined side walls offer advantages in the deposition of layers in subsequent process levels, such as a higher conductor track level in the metallization of the IC. This is because, unlike the steep side walls that typically arise during dry etching, the side surfaces of the material structured with lift-off can be coated using a broader range of processes. The surface also shows significantly fewer cracks in the topography , so that layers produced with rotation coating (e.g. photoresist layers for subsequent processes) can be applied more homogeneously. The process is therefore mainly used for structuring metallic layers. It enables the production of conductor tracks with structures in the micrometer range for the production of discrete components and also of (by today's standards) relatively simple integrated circuits with up to four conductor track levels.

Despite the advantages mentioned, the lift-off method for the production of the wiring levels of integrated circuits has not been able to prevail over structuring by means of dry etching ; Currently, the Damascene and Dual Damascene process is being used to a greater extent in this area . Reasons for this include the relatively low resolution and the more complex production of the structured sacrificial layer, since here attention must be paid to the compatibility of the chemical and physical properties of the sacrificial and target layer during the deposition and dissolution process.

Analogously to the production of conductor tracks, lift-off can also be used to produce bumps . These are metallic (usually a lead - tin alloy) contact elements for direct assembly of the chips, for example for tape automated bonding or flip-chip assembly . Here, too, there are several process variants that can also include copper contact surfaces, including copper diffusion barriers , produced using the lift-off process . Please refer to the literature for further information.

Nowadays, lift-off is used as a common process in the manufacture of components in the nanometer range (e.g. single electron transistors or micro- SQUIDs ). In most cases, electron beam lithography is used in combination with a positive photoresist, usually polymethyl methacrylate (PMMA). The method is limited primarily by the limited resolution of the lithographic structuring and the grain size of the deposited material. A line structure can be interrupted if the grain size is in the range of the line width.

literature

  • Zheng Cui: Nanofabrication: principles, capabilities and limits . Springer, 2008, ISBN 978-0-387-75576-2 , pp. 218–225 ( limited preview in Google book search - main source for the process variants ).
  • Friedemann Völklein, Thomas Zetterer: Practical knowledge of microsystem technology. Basics - Technologies - Applications; with 55 tables . 2., completely revised u. exp. Edition. Vieweg + Teubner, 2006, ISBN 3-528-13891-2 .
  • Kenneth A. Jackson, Wolfgang Schröter (Eds.): Handbook of Semiconductor Technology: Electronic structures and properties of semiconductors . Wiley-VCH, 2000, ISBN 3-527-29834-7 , pp. 587-590 .

Web links

Individual evidence

  1. ^ Zheng Cui: Nanofabrication: principles, capabilities and limits . Springer, 2008, ISBN 978-0-387-75576-2 , pp. 219 .
  2. ↑ Kenneth A. Jackson, Wolfgang Schröter (Ed.): Handbook of Semiconductor Technology: Electronic structures and properties of semiconductors . Wiley-VCH, 2000, ISBN 3-527-29834-7 , pp. 587-590 .
  3. ↑ Patent US2559389 : Method of Producing Precision Images. Registered on April 2, 1942 , inventors: Allan RA Beeber, David D. Jacobus, Carl W. Keuffel. ‌
  4. ^ M. Hatzakis: Electron Resists for Microcircuit and Mask Production . In: Journal of The Electrochemical Society . tape 116 , no. 7 , July 1, 1969, p. 1033-1037 , doi : 10.1149 / 1.2412145 .
  5. ^ Stanley Wolf, Richard N. Tauber: Silicon Processing for the VLSI Era. Volume 1: Process Technology . 2nd Edition. Lattice Press, 2000, ISBN 0-9616721-6-1 , pp. 535-536 .
  6. ↑ cf. u. a. Patent US3849136 : Aluminum Gap. Registered July 31, 1973 . ‌
  7. ↑ Helbert Helbert: Handbook of VLSI Microlithography, 2nd Edition: Principles, Tools, Technology and Applications . 2nd Edition. William Andrew Inc, 2001, ISBN 0-8155-1444-1 , pp. 730-733 .
  8. ↑ a b c d Friedemann Völklein, Thomas Zetterer: Practical knowledge of microsystem technology . 2., completely revised u. exp. Edition. Vieweg + Teubner, 2006, ISBN 3-528-13891-2 , pp. 96-97 .
  9. ↑ Kenneth A. Jackson, Wolfgang Schröter (Ed.): Handbook of Semiconductor Technology: Electronic structures and properties of semiconductors . Wiley-VCH, 2000, ISBN 3-527-29834-7 , pp. 234-235 .
  10. ^ William B. Glendinning, John N. Helbert: Handbook of VLSI microlithography: principles, technology, and applications . William Andrew, 1991, ISBN 0-8155-1281-3 , pp. 117-122 .
  11. ↑ a b Zheng Cui: Nanofabrication: principles, capabilities and limits . Springer, 2008, ISBN 978-0-387-75576-2 , pp. 220–221 ( limited preview in Google Book search).
  12. ↑ F. Radulescu et al .: Introduction of Complete Sputtering Metallization in Conjunction with CO 2 Snow Lift-Off for High Volume GaAs Manufacturing . In: Proc. GaAs MANTECH Conference . 2002 ( PDF ). PDF ( Memento of the original from May 13, 2015 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. Quoted from: Zheng Cui: Nanofabrication: principles, capabilities and limits . Springer, 2008, ISBN 978-0-387-75576-2 , pp.  @1@ 2Template: Webachiv / IABot / www.csmantech.org 223 ( limited preview in Google Book search).
  13. ↑ Kenneth A. Jackson, Wolfgang Schröter (Ed.): Handbook of Semiconductor Technology: Electronic structures and properties of semiconductors . Wiley-VCH, 2000, ISBN 3-527-29834-7 , Metallization and Liftoff Processes, pp. 581-590 .
  14. ^ Stanley Wolf: Silicon Processing for the VLSI Era. Volume 2: Process Integration . Lattice Press, 1990, ISBN 0-9616721-4-5 , pp. 285 .
  15. ↑ LJ Fried, J. Havas, JS Lechaton, JS Logan, G. Paal, PA Totta: A VLSI Bipolar Metallization Design with Three-Level Wiring and Area Array Solder Connections . In: IBM Journal of Research and Development . tape 26 , no. 3 , May 1, 1982, pp. 362-371 , doi : 10.1147 / around 263.0362 .
  16. ^ Herbert Reichl: Direct assembly . Gabler Wissenschaftsverlage, 1998, ISBN 3-540-64203-X , p. 18-45 .
  17. ^ Zheng Cui: Nanofabrication: principles, capabilities and limits . Springer, 2008, ISBN 978-0-387-75576-2 , pp. 219 ( limited preview in Google Book search).
This version was added to the list of articles worth reading on April 2, 2012 .