PowerPC

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PowerPC ( PPC ) is a 1991 American US by a consortium of Apple , IBM and Motorola (from 2004 Freescale , which in 2015 by NXP was acquired) - also briefly AIM called - specified microprocessor - Architecture . In 2005, marked by the withdrawal of several leading participants and the abandonment of the classic PC area as an application goal, the relevance of the platform for the publicly visible area decreased considerably. From 2006 the core series 2 was maintained under the name Power.org. In 2017 a well-maintained version 3 of the core with the attribute "OpenPOWER" is available.

The name PowerPC is an acronym , wherein power for P erformance o ptimization w ith e nhanced R ISC ( optimize performance through improved RISC ) and PC for P erformance C hip ( high-performance chip ) is.

Technology and areas of application

Development of the instruction set (PowerISA)

PowerPC was designed from the start as a 64-bit processor architecture based on RISC , although 32-bit versions are also available ( called “Subset” by IBM ). PowerPC can handle double and single precision floating point numbers and work in big-endian mode, although some processor models can switch to little-endian mode as an alternative . Almost all processors of the newer design also have the AltiVec vector unit developed by Motorola or the IBM equivalent VMX . AltiVec was introduced with the PowerPC 7400 aka PowerPC G4 . The last representative of the PowerPC family, which still comes from the AIM alliance, is the dual-core processor PowerPC 970MP and its single-core version PowerPC 970GX - marketed by Apple as PowerPC G5 , it is available together with its previous versions PowerPC 970 and 970FX with up to 2.7 GHz clock frequency for the last desktop and (as Xserve ) server computers built by Apple as Power Macintosh .

Newer versions of the PowerPC processor no longer have a generation designation (such as G3, G4, G5).

The Gekko (CPU in the Nintendo GameCube ) has special commands with which pairs of single-precision floating point numbers that are in floating point registers can be processed. The opcodes of the commands overlap with those of the AltiVec commands.

computer

PowerPC processors are u. a. in the IBM pSeries ( RS / 6000 ) and the IBM Blade JS20 and JS21 and in the Motorola - Power Stack used -Rechnern. Since 1996 Amiga computers have been based on PowerPC processors, and compatible systems such as the Pegasos computer from Genesi and the AmigaOne from Eyetech use it.

Apple used the processors to make their own computers between 1994 and 2006, but then switched to x86 processors from Intel. However, in April 2008 Apple bought the company PA Semi , which developed a particularly energy-saving variant of the G5 processors. The aim of this business was initially unclear, but later it turned out that Apple used the acquired expertise to develop its own processors.

Embedded Systems

PCI-104 module with PPC405 CPU

PowerPC processors are also used in many embedded systems .

For home users, these are, for example, digital receivers such as the d-box 2 (PPC823) or the Dreambox (PPC405), as well as game consoles such as Nintendo's GameCube , Wii and Wii U , Microsoft's Xbox 360 and (in the form of the cell in) Sony's PlayStation 3 .

The PowerPC architecture is also used in cars and in civil and military aviation and space travel. Several orbiters and landers sent to Mars are based on different PowerPC variants, for example the Mars Reconnaissance Orbiter uses a radiation-protected variant of the G3. The F-22 Raptor , the AN / ALR-93 or the AN / ALQ-135M also use PowerPC CPUs, especially in the area of signal processing .

History and future

The consortium was founded on the initiative of Apple , who were looking for a successor to the 680x0 processors from Motorola ( Freescale from 2004 , taken over by NXP Semiconductors in 2015 ). The POWER processor developed by IBM for their high-end workstations was an interesting candidate because of its powerful and expandable architecture, but it was far too expensive to manufacture, since at that time it was still a module with several chips. Motorola introduced the memory management and buffer unit of their 88000 RISC processors into the development (the 88k family was then discontinued, the 68k family still exists today as a microcontroller and also forms the basis for the compatible ColdFire family ) .

Simultaneously with the development of PowerPC processors, the reference platform PReP (was P owerPC Re ference P latform) created the competition to the established, Intel -based PCs should be. It then became apparent, however, that the alliance of the three companies did not agree on all issues; and the efforts, which were rather reserved anyway, later fizzled out.

PReP was later replaced by CHRP (Common Hardware Reference Platform). The youngest, commercially available member of this family was the IBM-certified Pegasos from Genesi , which was also sold by Freescale.

On June 6, 2005, Apple announced that it would abandon the PowerPC architecture and manufacture PC systems with Intel processors ( x86 ) in the future .

In an interview published December 6, 2005, Freescale CEO Michel Mayer et al. a. As a consequence of this, the decision to rename the PowerPC series if necessary and not to worry about the desktop / laptop market in further marketing.

At the 20th International Supercomputer Conference ISC 2005, held at the end of June 2005, it was also shown that six of the ten fastest computers in the world at the time were based on PowerPC, five of them on the PowerPC 440 ( eServer BlueGene ).

The focus of the application areas of the PowerPC architecture is thus shifting to both ends of the scale: the area of ​​embedded systems on the one hand and the high-performance server area on the other.

PowerPC generations and models (selection)

PowerPC 601 from IBM
The one PowerPC 603 from Motorola (XPC603FE75-2B)
A PowerPC 603e from Motorola (XPC603EFE117MJ)
PowerPC 604e 233 MHz, mounted on a Phase5 CyberStormPPC card for Amiga computers
Motorola XPC750ARX266PE
GEKKO in the GameCube

First generation G1

  • MPC601 - 50, 66, 80 and 100 MHz, 32 KByte Unified L1 cache, L2 cache up to 1 MByte; 0.6 µm manufacturing process (1993, used in the first Power Mac generation , among others )
  • MPC601 + - 110 and 120 MHz, otherwise like MPC601; 0.6 µm manufacturing process
  • MPC602 - especially for embedded applications (multiplexed data / address bus); 0.6 µm manufacturing process

Second generation G2

  • MPC603 - 66 to 80 MHz, 16 KByte (8 KByte instruction, 8 KByte data), L2 cache up to 1 MByte; especially for the mobile and “low cost” area; 0.5 µm manufacturing process
  • MPC603e - 100 to 200 MHz, from 166 MHz 32 KByte L1 cache (16 KByte instruction, 16 KByte data), L2 cache up to 1 MByte (larger L1 caches for better 68k emulator performance); 0.5 µm manufacturing process
  • MPC603ev - 225 to 300 MHz, 32 KByte L1 cache (16 KByte instruction, 16 KByte data), L2 cache up to 1 MByte; 0.35 µm manufacturing process
  • MPC604 - 100 to 180 MHz, 32 KByte L1 cache (16 KByte instruction, 16 KByte data), L2 cache up to 1 MByte; the 604 was available before the 603 (1994) and was the first high-end PowerPC; 0.5 µm manufacturing process
  • MPC604e - 166 to 233 MHz, 64 KByte L1 cache (32 KByte instruction, 32 KByte data), L2 cache up to 1 MByte; 0.35 µm manufacturing process
  • MPC604r - 250 to 375 MHz, 64 KByte L1 cache (32 KByte instruction, 32 KByte data), L2 inline cache up to 1 MByte; 0.25 µm manufacturing process (300 and 350 MHz model) or 0.35 µm (250 MHz model), code name "Mach 5" and "Helmwind"
  • MPC620 - 64 KByte L1 cache (32 KByte instruction, 32 KByte data), 1 to 128 MByte L2 cache; the first 64-bit PowerPC implementation ( not POWER)
  • x704 BiCOMOS PowerPC implementation by Exponential Technologies (never available)

Third generation G3

  • MPC750 - 200 to 366 MHz, 0.25 µm manufacturing process, code name "Arthur", introduced in 1997
  • MPC750CX - 350 to 550 MHz, 64 KByte L1 cache (32 KByte instruction, 32 KByte data), 256 KByte on-chip L2 cache, 0.18 µm manufacturing process; Code name "Sidewinder"
  • MPC750CXe - 400 to 700 MHz, 350 to 550 MHz, 64 KByte L1 cache (32 KByte instruction, 32 KByte data), 256 KByte on-chip L2 cache, L3 cache possible externally, 0.18 µm manufacturing process; Code name "Anaconda"
  • MPC750FX - 600 to 1000 MHz, 64 KByte L1 cache (32 KByte instruction, 32 KByte data), 512 KByte on-chip L2 cache, L3 cache possible externally, 0.13 µm manufacturing process; Code name "Sahara"
  • MPC750GX - 733 to 1000 MHz, 64 KByte L1 cache (32 KByte instruction, 32 KByte data), 1024 KByte on-chip L2 cache, L3 cache possible externally, 0.13 µm manufacturing process; Code name "Gobi"
  • Gekko 485 MHz (used in Nintendo GameCube )
  • RAD750 - Radiation-resistant version for space applications

Fourth generation G4

  • MPC7400 - 350 to 500 MHz, 32 KByte / 32 KByte data / instruction L1 cache, maximum 2 MByte L2 cache (ECC and non-ECC), power loss max. 11 watts, first PowerPC with AltiVec , code name "Max"
  • MPC7410 - 400 to 550 MHz, 32 KByte / 32 KByte data / instruction L1 cache, maximum 2 MByte L2 cache (ECC and non-ECC), power loss max. 11 watts
  • MPC7441 - 600 and 700 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 256 KByte L2 cache on chip, maximum 2 MByte L3 cache; Low power version of the 7450/7451
  • MPC7445 - 600 to 1000 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 256 KByte L2 cache on chip, power loss max. 26 watts
  • MPC7447 - 600 to 1267 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 256 or 512 KByte L2 cache on chip, power loss max. 26 watts, no L3 cache
  • MPC7447A - 600 to 1420 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 512 KByte L2 cache on chip, power loss max. 29 watts
  • MPC7448 - 600 to 2000 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 1024 KByte L2 cache with ECC on chip, power loss approx. 10 watts at 1.5 GHz
  • MPC7450 - 533 to 867 MHz, 32 KByte / 32 KByte data / instruction L1 cache, code name "Voyager"
  • MPC745 - 300 to 350 MHz, 32 KByte / 32 KByte data / instruction L1 cache, power loss max. 5.3 watts
  • MPC7451 - 533 to 867 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 256 KByte L2 cache on chip, maximum 2 MByte L3 cache
  • MPC7455 - 600 to 1425 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 256 KByte L2 cache on chip, maximum 2 MByte L3 cache, power loss max. 45 watts, code name "Apollo"
  • MPC7457 - 600 to 1333 MHz, 32 KByte / 32 KByte data / instruction L1 cache, 512 KByte L2 cache on chip, maximum 2 MByte L3 cache, power loss max. 25 watts
  • MPC755 - 300 to 400 MHz, 32 KByte / 32 KByte data / instruction L1 cache, maximum 1 MByte L3 cache, power loss max. 8 watts

Fifth generation G5

  • 970 - 64-bit implementation, derived from the IBM POWER4, extended by VMX (IBM's equivalent to Motorola's AltiVec ) with 1.4 GHz, 1.6 GHz, 1.8 GHz, and 2.0 GHz clock frequency (2003)
  • 970FX - with up to 2.5 GHz clock frequency (2004), overclocked to 2.7 GHz by Apple
  • 970MP - Dual Core with 1.4 to 2.5 GHz clock (2005); Code name "Antares"
  • 970GX - up to 3 GHz clock. At 1.6 GHz 16 W power consumption, 85 W at 3 GHz (2006)

Operating systems

Most current versions of the listed operating systems today (as of 2017) no longer have (official) support for the PowerPC architecture, as the PowerPC processor can no longer be found in current desktop systems, workstations and servers . However, there are versions for embedded systems and unofficial ports for older PowerPC desktop computers (such as the Apple Power Macintosh range ).

Web links

Commons : PowerPC  - collection of pictures, videos and audio files

Individual evidence

  1. ^ Daniel Tabak: RISC Systems and Applications . Research Studies Press, University of California 1996, ISBN 978-0-471-96027-0 , pp. 148 (English, 435 p., Limited preview in the Google Book Search): “It should be noted that the PowerPC architecture was designed from the beginning with future 64-bit implementations in mind. The PowerPC architecture was defined as a 64-bit architecture with a 32-bit subset. "
  2. ↑ Stephan Ehrmann: WWDC: Apple changes to Intel architecture. In: Heise online . June 6, 2005 (4th update). Retrieved March 9, 2016.
  3. ↑ Andreas Stiller: Top500 of supercomputers: IBM dominates. In: Heise online . June 22, 2005 (report on the 20th international supercomputer conference “ ISC 2005” in Heidelberg). Retrieved March 9, 2016.
  4. ↑ Carsten Meyer: Exponential shows X704-Mac with 450 MHz. In: Heise online . March 15, 1997 . Retrieved March 9, 2016.
  5. ↑ http://www.sciopta.com SCIOPTA; RTOS.