Technology node

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The term technology node ( english technology node ) referred to in the semiconductor technology a milestone for the definition of a manufacturing process generation and refers mainly to the smallest photolithographically manufacturable structure size . Since 1997 it has been defined by the International Technology Roadmap for Semiconductors (ITRS). However, the term itself is very abstract and only roughly describes the technological progress in the industry. The technologies used differ not only between the various manufacturers at a technology node, but also between the products of a manufacturer (especially for contract manufacturers, so-called foundries ) at the same technology node. Furthermore, there is no fixed relation to the gate length.

description

The technology node generation is described in terms of a numerical value, which refers to the so-called " half pitch " (dt. Half pitch / spacing ) of DRAM relates -Bauelementen, for example, to half the distance measure of two conductor tracks or contact holes of a periodic structure in the first wiring plane . Typical specifications are “65 nm technology nodes” or “65 nm technology” for short (sometimes also “65 nm technology” or “65 nm production”). Before 1999, instead of the current specification in nanometers, specification in micrometers was used, for example 0.25 µm technology or 0.8 µm technology.

Since the value of the technology node only specifies half the distance between dense line or trench structures, the minimum gate length of a field effect transistor can be smaller and cannot be precisely determined using the technology node. For example, the gate length in a 65 nm process can be 50 nm or less. The value of the technology node therefore does not directly identify the smallest structure that can be produced with photolithography .

It should also be noted that the specification of a specific technology node can only provide a rough classification of the manufacturing techniques used. In relation to a manufacturer, components of a technology node have largely been manufactured using the same techniques. Such a comparison between the products of different manufacturers is no longer possible by the end of the 1990s at the latest, as the manufacturing techniques sometimes differ greatly. Examples of this are the use of copper instead of aluminum in the wiring levels or the use of so-called high-k + metal gate technology .

The classification of the individual microelectronic components is also not mandatory, so that, for example, some manufacturers of memory modules or graphics chips often deviate from this grid or do not use such a classification and use structure sizes in between.

history

In the early phase of microelectronics up to the 1980s, new technology nodes were introduced without taking defined scaling ratios into account . As structures became smaller, it became necessary to find better definitions of the technology nodes with a specific target size for the scaling factor. A factor of 1 / √2 = 0.7 was determined between successive nodes, i.e. a 30 percent reduction in the side dimensions, which means an approximate halving of the area. However, this factor has not been applied consistently, especially in recent years. For this reason, there were also changes in the schedule for the coming technology nodes, e.g. B. with ITRS 2001. Intermediate levels such as the 80 nm or 40 nm nodes were also introduced in the DRAM sector.

Overview

List of technology nodes ( note: intermediate steps in italics )
Node year Representative (selection) Innovations (manufacture, masks, operating voltage, ...)
10 µm 1971 Intel 4004 , Intel 8008 , Fairchild PPS-25 ,
Rockwell PPS-4 		4-bit register (later also 8-bit), PMOS - silicon gate technology
06 µm 1974 Intel 8080 NMOS silicon gate technology
03 µm 1975 Intel 8085 , Intel 8086 Transition to an operating voltage of +5 V (instead of + 5 / −5 / + 12 V)
01.5 µm 1982 Intel 80286
01 µm 1985 Intel 80386 CMOS silicon gate technology
00.8 µm 1989 Intel Pentium 60 (P5) 5.0 V for the last time
00.6 µm 1994 Intel Pentium 100 (P54C) 3.3V
00.35 µm 1995 Intel Pentium 133 (P54CS) the last time an operating voltage: 3.3 V
00.3 µm 1997 AMD K6 (Model 6) Split operating voltage 2.8-3.2 V for core + 3.3 V for IO
00.25 µm 1998 Intel Pentium 200 MMX (P55),
Intel Pentium II , AMD K6 (Model 7) 		2.0-2.8V
180 nm 1999 Pentium III (Coppermine) Use of copper instead of aluminum in the wiring level, which also involved the introduction of additional process steps to create the necessary copper diffusion barrier.
130 nm 2002 Pentium 4 (Northwood) ,
AMD Athlon 64 		Intel uses fluorine - doping , the relative permittivity of 4.0 to 3.6 in the wiring layer to press. AMD uses "Black Diamond" (a carbon-doped silicon dioxide from Applied Materials ) as a low-k dielectric
090 nm 2004 Pentium 4 (Prescott) ,
Athlon 64 (Winchester) 		Stretched silicon for the first time in AMD processors and Intel. Intel uses low-k dielectric ( carbone-doped oxide , dt., Carbon-doped silicon dioxide ") with a k-value of below 3.0 in the wiring layer.
065 nm 2006 Core 2 from Intel Intel introduces the double patterning process to increase the resolution at critical levels.
045 nm 2008 Penryn CPUs of the Core 2 from Intel Introduction of high-k + metal gate technology for Intel processors (gate-load approach). Immersion lithography in 2009 on AMD processors .
040 nm 2009 Radeon HD 5000 GPUs manufactured by TSMC Introduction of a new low-k dielectric with a k value of 2.5 in the wiring level at TSMC. Immersion lithography in graphics processors.
034 nm 2009 NAND flash from IM Flash Technologies
and Samsung Semiconductor 		In addition to the immersion lithography from the previous process, Samsung has added self-aligned (spacer) double pattering (SaDP).
032 nm 2010 Westmere CPUs of the Core i7 / i5 / i3 from Intel Intel is now also using immersion lithography in production, and AMD's contract manufacturer Globalfoundries is now also introducing the double patterning process . Introduction of high-k + metal gate technology for AMD processors (gate-first approach) in 2011.
024-28 nm 2011 NAND flash from Samsung
Semiconductor, IM Flash
Technologies, Hynix and Toshiba .
Radeon HD 7000 GPUs manufactured by TSMC 		The largest contract manufacturer TSMC is also introducing high-k + metal gate technology (gate load) with its 28 nm process.
022 nm 2012 Ivy Bridge -CPUs of the
Core i7 / i5 / i3 from Intel 		Introduction of multigate field effect transistors into the high volume production of logic products by Intel.
019-21 nm 2012 NAND flash from Samsung
Semiconductor, IM Flash
Technologies and Toshiba
015 nm 2014 NAND flash from SanDisk and Toshiba
014 nm 2014 Broadwell , processor from Intel
010 nm 2017 A10X Fusion , Apple's one-chip system
07 nm 2018 Apple A12 Bionic , Apple's one-chip system; HiSilicon Kirin 980; Vega 20, Ryzen 3000 and RX 5700 from AMD EUV lithography ("extreme ultra-violet") with a wavelength of 13.5 nm by Samsung
5 nm 2020 Apple A14 Bionic , one-chip system from Apple and the Qualcomm Snapdragon 875 SoC will be produced by TSMC from June 2020

More details

The following important information is missing from this article or section:
Development beyond 22 nm
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First semiconductors

The first semiconductor components manufactured did not use mask technology, but were built mechanically. The first transistor was a tip transistor in which two metal tips were applied to a substrate. An important representative was the alloy transistor , in which two indium beads were applied to an n-doped substrate, and the epitaxial transistor .

50 µm technology node

The planar transistor was introduced in the mid-1960s . The original structure size was 50 µm. In addition to individual transistors, smaller ICs such as logic gates and the first operational amplifiers were built with them.

10 µm technology node

The 10 µm technology node was achieved in 1971 with the Intel 4004 and in 1972 with the Intel 8008. The exposure takes place with the mercury G line of 435.83 nm. Wafers used for this had sizes of 2 inches (50.8 mm).

6 µm technology node

The 6 µm technology node was reached in 1974 with the Intel 8080. Later processors like the Zilog Z80 used slightly smaller 5 µm and 4 µm processes.

3 µm technology node

The 3 µm technology node was achieved in 1977 with the Intel 8085. Further representatives are the Intel 8086 and 8088 as well as the Motorola MC68000.

1.5 µm technology node

1 µm technology node

The 1 µm technology node was achieved in 1985 with the Intel 80386. The exposure was switched from the mercury G line of 435.83 nm to the mercury i-line of 365.01 nm.

800 nm technology node

600 nm technology node

350 nm technology node

250 nm technology node

Intel used 200 mm wafers and 5 metallization layers for the 250 nm technology node.

180 nm technology node

The 180 nm technology node was introduced in 1999 by leading semiconductor manufacturers such as Intel, Texas Instruments, IBM and TSMC. Here, some manufacturers for the first time led ArF - excimer laser with a wavelength of 193 nm (instead of KrF excimer laser with 248 nm) for the production of critical levels (gate contacts, etc.), such as Intel Pentium III (Coppermine). Some manufacturers (especially foundries ) will use this technology until 2011, e.g. B. Microchip Technology and Parallax Propeller , because the structure sizes are sufficient for the desired products, for example in the automotive sector. In addition, the processes are mature and can therefore with a high yield (Engl. Yield ) are driven.

130 nm technology node

Based on the research results of the IBM Alliance , AMD introduced low-k dielectrics for the 130 nm technology node (2002) for the first time ( k stands for the relative permittivity of a material) as insulation between the upper conductor track levels (approx.level 8 to 11) a. Furthermore, so-called silicon-on-insulator wafers (SOI wafers) were used for the first time (2003) instead of bulk silicon wafers. The advantages of these more expensive substrates are above all a higher switching speed of the transistors and the reduction of leakage currents between different (electrically) active areas.

90 nm technology node

The 90 nm technology node was first introduced into industrial production (first commercial products) in 2002. For the production of the critical levels, the photolithographic processes with ArF excimer lasers prevailed, as no other processes with the necessary resolution were available. In addition, AMD introduced expanded silicon to improve charge carrier mobility in its products for the first time .

65 nm technology node

45 nm technology node

The 45 nm technology node was first used in production by Intel and Matsushita in 2007-2008 . Other manufacturers such as AMD , IBM and Samsung followed a little later.

The most important change in production was the introduction of high-k materials and the use of a metal gate electrode by Intel (cf. high-k + metal gate technology ). This allows the leakage currents due to tunnel effects on the transistor to be significantly reduced.

32 nm technology node

While either immersion lithography or the double patterning process was used in the previous technology node, all manufacturers now have to use both technologies in order to be able to manufacture these structures reliably. Vendors such as TSMC who skip the process use both technologies in the 28nm half-node process. High-k + metal gate technology is widely used in the manufacture of main and graphics processors as well as APUs .

The first processors to be mass-produced in 32 nm technology were Intel's Core i3 and Core i5 processors, which were released in January 2010. Competitor AMD did not follow suit until over a year later, selling its first commercially available 32 nm processors. These are "Llano" -based models from AMD's Fusion series. In contrast to Intel, SOI substrates were used here again.

22 nm technology node

With the introduction of the 22 nm technology node, some manufacturers, primarily Intel, want to change the type of transistor used in the large-volume production of integrated circuits. They walk away from decades of used planar process towards so-called multi-gate field effect transistors (engl. Multiple gate field-effect transistor , MuGFET) such as tri-gate FETs and FinFETs . The first processors to use this technology are the 3rd generation Intel Core i processors . Analyzes of a processor cross-section showed that Intel apparently uses a gate pitch of 90 nm, which corresponds to a half pitch of 45 nm. The assignment of the technology node of these Intel processors thus deviates significantly from the earlier classification using the half-pitch.

However, not all semiconductor manufacturers are pursuing this conversion of the transistor type, so Globalfoundries and TSMC - two of the three largest contract manufacturers for semiconductor products, so-called foundries , and also technology drivers - have announced that they will also be serving their customers in the 22 nm and 20 nm technology nodes Will offer processes in planar technology. The increasing leakage currents should be manageable here, for example, by means of new SOI substrates in which a very thin semiconductor layer on an insulator can be completely depleted ( full depletion silicon-on-insulator , fdSOI)

14 nm technology node

10 nm technology node

In 2016, Intel planned the first micro-architecture in a 10 nm manufacturing process as the successor to the Skylake micro-architecture. These processors were originally supposed to appear in 2017, but the date has been postponed repeatedly due to technical problems. Problems with 193 nm immersion lithography, which Intel still wants to use for these small structures, are also cited as the reason. As a consequence, the stable 14 nm manufacturing process will be optimized several times until 2020 the first 10 nm processors of the Ice Lake generation will appear on the market. In the meantime, a model of the Cannon Lake architecture is being manufactured in 10 nm, but only appears in sample numbers and without integrated processor graphics. Intel compares its 10 nm process in terms of achievable transistor density with the 7 nm process from TSMC.

7 nm technology node

Since the beginning of 2019, 7 nm processes have been offered by two foundries: Samsung and TSMC.

A major innovation in manufacturing technology at this technology node is the introduction of the long-announced EUV lithography ("extreme ultra-violet") with a wavelength of 13.5 nm by Samsung. It replaces the established 193 for the most critical lithography steps -nm- immersion lithography , which in the last technology nodes could only be used in combination with multiple structuring techniques . Actually, this step had already been expected several years earlier, as it was expected that the resolution limit for optical imaging would represent a physical limit due to diffraction effects in the desired reduction in size of the structures using established radiation sources such as the most recently 193 nm ArF excimer laser. Numerous compensation techniques were invented and introduced sooner than the series production of EUV lithography, but these are complex and costly for the most critical levels of the 7 nm processes. Together with the recent progress made by the system manufacturer ASML and its suppliers with regard to the productive use of EUV lithography, it is now sufficiently profitable for production compared to the established processes. TSMC has also announced that it will use EUV lithography in its second 7 nm production generation.

5 nm technology node

In March 2019, TSMC starts the risk production (pre-series after the general qualification, mostly for samples and to find weak points in real products) of its 5 nm manufacturing process, since the 2nd quarter of 2020 the start of the regular (mass) production has been running in this Process and is therefore the world leader in this miniaturization level. EUV lithography is used for exposure. TSMC specifies a manufacturing density of 171.3 million transistors / mm². Intel compares its (not yet running) 7nm manufacturing process with TSMC's 5nm process in terms of transistor density. Since June 2020 the Apple A14 Bionic SoC , the Qualcomm Snapdragon 875 SoC and the Qualcomm Snapdragon X60 modem have been mass-produced at TSMC in 5 nm.

4 nm technology node

The largest contract manufacturer in the semiconductor industry, TSMC, is said to have made further improvements to the N5 in mid-2020 and to have already prepared the 4 nm technology node (N4) expected for 2022.

3 nm technology node

2 nm technology node

1.5 nm technology node

1.4 nm technology node

At the end of 2019, at the IEEE International Electron Devices Meeting, it was announced that Intel plans to begin mass production in the 1.4 nm technology node in 2029.

1.0 nm technology node

literature

  • Paolo Gureini: The 2002 International Technology Roadmap Semiconductors (ITRS) . In: Howard R. Huff, László Fábry, S. Kishino (Eds.): Semiconductor silicon 2002 Volume 2: Proceedings of the Ninth International Symposium on Silicon Materials Science and Technology . The Electrochemical Society, 2002, ISBN 978-1-56677-374-4 , pp. 9 ff . ( limited preview in Google Book search).

Web links

Individual evidence

  1. ^ HR Huff, L. Fabry, S. Kishino: Semiconductor silicon 2002. Volume 2 . The Electrochemical Society, ISBN 978-1-56677-374-4 , pp. 4-9 .
  2. ↑ a b Albert Lauchner: low-k copper wiring . tecchannel, February 20, 2003
  3. ↑ a b Parwez Farsan:AMD uses strained silicon in production. ComputerBase, August 22, 2004 (news item).
  4. ↑ Thomas Huebner: First details on 90 nm technology for Pentium 4 successors . ComputerBase, August 14, 2002 (news item).
  5. ↑ Christof Windeck: Low-k dielectrics are widely used in chip production . heise online, February 5, 2004 (news item).
  6. ↑ Andreas Stiller: Intel's 90 nm process with "stressed" silicon . heise online, August 13, 2002 (news item).
  7. ↑ a b Intel (Ed.): 45 nm High-k + Metal Gate Strain-Enhanced Transistors .
  8. ↑ a b Anand Lal Shimpi: AMD Phenom II X4 940 & 920, 45nm Anandtech, August 1, 2009 (article).
  9. ↑ a b Jürgen Schmidt: TSMC: Scarce production capacities at 40 nm . Hardware information, February 27, 2010 (news item).
  10. ↑ Samsung touts 30 nm NAND flash using double-patterning  ( page no longer available , search in web archives )  Info: The link was automatically marked as defective. Please check the link according to the instructions and then remove this notice. . @1@ 2Template: Dead Link / www.electroiq.com  ElektroIQ, October 23, 2007 (news item).
  11. ↑ Onkel_Dithmeyer: GlobalFoundries brings gate load from 20 nm . Planet 3DNow !, January 19, 2011 (news item).
  12. ↑ Christof Windeck: Samsung manufactures NAND flash chips of the "20 nanometer class". heise online, May 19, 2011, accessed on May 24, 2011 .
  13. ↑ Jürgen Schmidt: Hynix: mass production of 20 nm NAND flash . Hardware information, August 10, 2010 (news item).
  14. ↑ Volker Rißka: SanDisk and Toshiba start 15 nm flash memory production. Computerbase.de, April 23, 2014, accessed April 25, 2014 .
  15. ↑ a b c Samsung Electronics starts production of EUV based 7 nm chips. Retrieved February 13, 2019 .
  16. ↑ a b Hannes Brecher: TSMC starts producing 5 nm chips. In: https://www.notebookcheck.com/ . June 20, 2020, accessed June 23, 2020 .
  17. ↑ Intel Pushes Lithography Limits, Part II
  18. ^ Antone Gonsalves: informationweek.com . InformationWeek, January 7, 2010.
  19. ↑ David Kanter: Real World Technologies - Intel's 22 nm Tri-Gate Transistors. May 5, 2011, accessed April 16, 2012 .
  20. ↑ Rick Merritt: Analysts start Intel Ivy Bridge CPU teardown. April 11, 2012, Retrieved April 16, 2012 .
  21. ↑ Ron Wilson: The next transistor: planar, fins, and SOI at 22 nm. July 19, 2011, accessed April 16, 2012 .
  22. ↑ Ron Wilson: The next transistor: planar, fins, and SOI at 22 nm - Fins and the rest of us. July 19, 2011, accessed April 16, 2012 .
  23. ↑ TSMC kicks off volume production of 7 nm chips. Retrieved February 13, 2019 .
  24. ↑ https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/
  25. ↑ Sven Bauduin: Foundry: 4 nm chip production at TSMC already in preparation. In: computerbase.de. June 10, 2020, accessed June 17, 2020 .
  26. ↑ Michael Eckstein: After the 10 nm debacle: Intel's ten-year roadmap to the 1.4 nm process node. In: elektronikpraxis.vogel.de. December 16, 2019, accessed June 17, 2020 .