ARM Cortex-A

from Wikipedia, the free encyclopedia

ARM Cortex-A refers to a series of microprocessor design company ARM Holdings Plc , the complex to perform computing tasks are provided, and as IP core available licensees. The suffix "A" stands for applications (dt. Applications ) and to the processors so called suitable hardware basis for the execution of complex operating systems identification and different software applications. The CPUs are based on the ARM architecture and implement the instruction set architecture ( ISA ) ARMv7-A or ARMv8-A. The IP cores of the ARM Cortex-A series are advertised as an energy-efficient high-performance platform and licensed by numerous chip manufacturers around the world to design their own single-chip systems . Corresponding SoCs are used in smartphones , mobile computers, digital televisions and set-top boxes , among other things .

ARM Cortex-A8

Compared to its predecessor, the ARM11 , the Cortex-A8 presented in 2005 is a 32-bit superscalar single-core dual issue design that can execute around twice the number of instructions per clock cycle. It has a computing power of 2.0  DMIPS / MHz and has a 32 kB L1 cache each for commands and data as well as a 512 kB L2 cache. The clock frequencies in a 65 nm process from TSMC range between 600 MHz and more than 1 GHz. The pipeline length is 13 stages.

The Cortex-A8 was the first core from the Cortex family to be implemented in numerous consumer electronics devices.

properties

crisps

The system-on-chips (SoC) with implemented Cortex-A8 core include: a .:

ARM Cortex-A9

The ARM Cortex-A9 introduced in 2007 is a 32-bit microprocessor that implements the ARMv7-A architecture. It can execute 32-bit ARM commands, 16- and 32-bit thumb commands and 8-bit Java bytecodes. The Cortex-A9 is a superscalar dual issue out of order design. The processor has a computing power of 2.5  DMIPS / MHz and has a 32 kB L1 cache for commands and data as well as a 128 kB to 8 MB L2 cache. The clock frequencies in a 45 nm process from TSMC range between 800 MHz and 2 GHz. The pipeline length is 8 stages. The Cortex-A9 is the first member of the Cortex-A family that can be used in both uniprocessor and multiprocessor configurations . The multiprocessor ARM Cortex-A9 MPCore has up to four cache-coherent Cortex-A9 processor cores that are under the control of the Snoop Control Unit (SCU). The SCU ensures the L1 data cache coherence.

properties

  • NEON SIMD extensions (optional)
  • VFPv3 floating point unit
  • Thumb-2 instruction set
  • TrustZone security extensions
  • Jazelle DBX support for executing Java code
  • Jazelle RCT.

crisps

MediaTek MT6575A

The system-on-chips (SoC) with implemented Cortex-A9 cores include a .:

ARM Cortex-A5

The ARM Cortex-A5 MPCore presented in 2009 is a 32-bit multicore processor with up to 4 cache-coherent Cortex-A5 cores, each of which implements the ARMv7-A instruction set. It is a single issue in order design. It has a computing power of 1.57  DMIPS / MHz and has a 4-64 kB L1 cache for commands and data as well as an optional 16 kB to 1 MB L2 cache. The clock frequencies in a 40 nm process from TSMC reach up to 1 GHz. The pipeline length is 8 stages. The Cortex-A5 was introduced as the more energy-efficient successor to the ARM9 and ARM11 cores for entry-level and mid-range mobile devices. Compared to these older cores, the Cortex-A5 offers the advantage of the more modern instruction set ARMv7 compared to ARMv4 / v5 (ARM9) or ARMv6 (ARM11) as well as VFPv3 and NEON- SIMD extensions.

properties

crisps

The system-on-chips (SoC) with implemented Cortex-A5 cores include a .:

ARM Cortex-A15

The ARM Cortex-A15 MPCore presented in 2010 is a 32-bit multicore processor with up to 4 cache-coherent Cortex-A15 cores, each of which implements the ARMv7-A instruction set. It is a 3-way, superscalar out-of-order design. It has a computing power of 3.4  DMIPS / MHz and has a 32 kB L1 cache for commands and data as well as a 128 kB to 2 MB L2 cache. The clock frequencies in a 28 nm process from TSMC reach up to 2.5 GHz. The pipeline length is 15 stages. With Big.LITTLE processing, a cluster consisting of Cortex-A15 cores is implemented on one chip with a cluster of 1 to 4 Cortex-A7 cores for energy-saving reasons, each of which processes these alternately depending on the software's computing power requirements.

properties

  • 40-bit physical address space for up to 1 TB RAM, one 32-bit address space can be addressed per process
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent switching matrix)
  • DSP and NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware virtualization support
  • Thumb-2 instruction set
  • TrustZone security extensions
  • Jazelle DBX support for executing Java code
  • Jazelle RCT

crisps

The system-on-chips (SoC) with implemented Cortex-A15 cores include a .:

ARM Cortex-A7

Mediatek MT6582V

The ARM Cortex-A7 MPCore introduced in 2011 is a 32-bit multicore processor that implements the ARMv7-A instruction set. It is a partial dual issue in order design. It has a computing power of 1.9  DMIPS / MHz and has two separate, 8-64 kB L1 caches as well as an optional 128 kB to 1 MB L2 cache. The two L1 caches are used to buffer commands and data independently of one another. The pipeline length is 8 stages. The clock frequencies in a 28 nm process from TSMC reach up to 2 GHz at the licensee Mediatek . On the ARM side, up to 4 processor cores per cluster are provided, with AMBA 4 technology several coherent SMP clusters can be combined with one another. The Cortex-A7 appears both alone as a more energy-efficient successor to the Cortex-A8 and in Big.LITTLE processing. Here, a cluster consisting of 1-4 Cortex-A7 cores is implemented together on one chip with a cluster of 1 to 4 Cortex-A15 cores for reasons of higher computing power, each of which processes these alternately depending on the software's computing power requirements.

properties

  • 40-bit physical address space for up to 1 TB RAM, one 32-bit address space can be addressed per process
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent switching matrix)
  • DSP and NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware virtualization support
  • Thumb-2 instruction set
  • TrustZone security extensions
  • Jazelle DBX support for executing Java code
  • Jazelle RCT

crisps

The system-on-chips (SoC) with implemented Cortex-A7 cores include a .:

ARM Cortex-A53

The ARM Cortex-A53 MPCore introduced in 2012 is a 64-bit multicore processor with up to 4 cache-coherent Cortex-A53 cores, each of which implements the ARMv8-A instruction set. It is a partial dual issue in order design. It has a computing power of 2.3  DMIPS / MHz and has an 8-64 kB L1 cache for commands and data as well as an optional 128 kB to 2 MB L2 cache. In a SoC design by the manufacturer MediaTek, produced in the 16nm FinFET + process , the processor reaches a clock frequency of up to 2.6 GHz. The pipeline length is 8 stages. The Cortex-A53 appears both alone and with Big.LITTLE processing. Here, a cluster consisting of 1-4 Cortex-A53 cores is implemented together on one chip with a cluster of 1 to 4 Cortex-A57 cores for reasons of higher computing power, each of which processes these alternately depending on the software's computing power requirements.

properties

  • Operating modes AArch64 (64-bit) and AArch32 (32-bit and ARMv7 backward compatibility)
  • 40-bit physical address space for up to 1 TB RAM, one 32-bit address space can be addressed per process
  • extended NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware encryption ( AES , SHA-1 , SHA2-256)
  • Hardware virtualization support
  • TrustZone security extensions
  • Thumb-2 instruction set
  • Jazelle DBX support for executing Java code
  • Jazelle RCT

crisps

The system-on-chips (SoC) with implemented Cortex-A53 cores include: a .:

  • Allwinner A64, H5, H6
  • Amlogic S805X, S905 (L / X / D / W / Z), S905X2, S905Y2, S912, S922X, A112, A113, A311D
  • Broadcom BCM2837 ( Raspberry Pi 2 Model B v1.2 and 3 Model B), BCM2837B0 (Raspberry Pi 3 Model A + and B +)
  • HiSilicon Kirin 620, 650, 655, 658, 710, 930, 935, 950, 955, 960, 970
  • Mediatek MT6732, MT6735, MT6750, MT6752, MT6753, MT6755, MT6757, MT6795, MT6797 (T), MT6799, MT8165, MT8173 (C), MT8176, MT8732, MT8735, MT8752
  • Rockchip RK3368, RK3399
  • Samsung Exynos 5433, 7420, 7570, 7578, 7580, 7870, 7880, 8890, 8895
  • Qualcomm Snapdragon 410, 415, 420, 425, 430, 435, 610, 615, 616, 617, 625, 630, 650, 652, 808 and 810
  • Xilinx Zynq UltraScale + MPSoC

ARM Cortex-A57

The ARM Cortex-A57 MPCore, also presented in 2012, is a 64-bit multicore processor with up to 4 cache-coherent Cortex-A57 cores, each of which implements the ARMv8 instruction set. It is a 3-way, superscalar out-of-order design. It has a computing power of 4.1  DMIPS / MHz and has a 48/32 kB L1 cache for commands and data as well as a 512 kB to 2 MB L2 cache. The clock frequencies in a 20 nm process from TSMC will reach 2.5 GHz. The pipeline length is 15 stages. With Big.LITTLE processing, a cluster consisting of Cortex-A57 cores is implemented on one chip with a cluster of 1 to 4 Cortex-A53 cores for reasons of energy saving, which alternately process these depending on the requirements of the software on the computing power.

properties

  • Operating modes AArch64 (64-bit) and AArch32 (32-bit and ARMv7 backward compatibility)
  • 4 cores per cluster (AMBA-4 ACE and AMBA-5 CHI are supported)
  • 44-bit physical address space
  • extended NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware encryption ( AES , SHA-1 , SHA2-256)
  • Hardware virtualization support
  • TrustZone security extensions
  • Thumb-2 instruction set
  • Jazelle DBX support for executing Java code
  • Jazelle RCT

crisps

The system-on-chips (SoC) with implemented Cortex-A57 cores include: a .:

ARM Cortex-A12 / A17

The ARM Cortex-A12 MPCore presented in 2013 is a 32-bit multicore processor with up to 4 cache-coherent Cortex-A12 cores, each of which implements the ARMv7-A instruction set. It is a dual issue out of order design. It has a computing power of 3.0  DMIPS / MHz and has a 32-64 kB L1 cache for commands, a 32 kB L1 cache for data and a 256 kB to 8 MB L2 cache. The clock frequencies in a 28 nm process from TSMC reach up to 2 GHz. The pipeline length is 10 stages. The Cortex-A12 should succeed the Cortex-A9 and was developed for production with a structure size of 28 nm. The higher computing power / MHz (3.0 instead of 2.5 DMIPS / MHz) was u. a. achieved through a more complex out-of-order design, a larger jump history table, more execution units (7 instead of 3) and a fully integrated L2 cache. At the time of the presentation, the processor design should achieve 40% higher computing power compared to the ARM Cortex-A9. With Big.LITTLE processing, a cluster consisting of Cortex-A12 cores is implemented on one chip with a cluster of 1 to 4 Cortex-A7 cores for energy-saving reasons, each of which processes these alternately depending on the software's computing power requirements.

The Cortex-A12 design was further developed by ARM in 2014 to the level of performance of the Cortex-A17 MPCore presented in February 2014. In September 2014, ARM announced that the Cortex-A12 would no longer be marketed as a CPU design. The ARM Cortex-A17 MPCore is intended as a replacement. According to ARM, the Cortex-A17 should be around 60% faster than the Cortex-A9.

properties

  • 40-bit physical address space for up to 1 TB RAM, one 32-bit address space can be addressed per process
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent switching matrix)
  • DSP and NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware virtualization support
  • Thumb-2 instruction set
  • TrustZone security extensions
  • Jazelle DBX support for executing Java code
  • Jazelle RCT

crisps

  • Rockchip RK3288

ARM Cortex-A72

The ARM Cortex-A72 MPCore introduced in 2015 is like the A57 a 64-bit multicore processor with up to four cache-coherent Cortex-A72 cores, each of which implements the ARMv8 instruction set. It is a three-way, superscalar out-of-order design with a 15-step pipeline. According to ARM, the A72 delivers "up to 50% higher computing power" than the A57 at the same clock rate and has a 48/32 kB L1 cache for commands and data as well as a 512 kB to 2 MB L2 cache. The target production process is to be 16 nm FinFET from TSMC , in which clock frequencies of up to 2.3 GHz are achieved; ARM specifies the theoretical maximum clock rate of 2.5 GHz. In Big.LITTLE processing, a cluster consisting of Cortex-A72 cores is implemented on one chip with a "cluster" of one to four Cortex-A53 cores for energy saving reasons, each of which alternates depending on the software's computing power requirements work off. It should be noted that the calculation of the computing power compared to the A57 assumes a 16 nm FinFET process, while the figures for the A57 come from the 20 nm process. A significant part of the increase is therefore achieved purely in terms of production technology through Moore's Law . The basis for the new design was the Cortex-A57, which is optimized in numerous blocks, such as branch prediction, latency times for floating point operations and cache management. The space requirement sank by the 28 nm production from 3.6 mm² (A57) to 3.3 mm².

properties

  • 40-bit physical address space for up to 1 TB RAM, one 32-bit address space can be addressed per process
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 500 (an AMBA-4 coherent switching matrix, AMBA-5 CHI is supported)
  • DSP and NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware virtualization support
  • Thumb-2 instruction set
  • TrustZone security extensions
  • Jazelle DBX support for executing Java code
  • Jazelle RCT
  • Hardware encryption (AES, SHA-1, SHA-256) optional

crisps

The system-on-chips (SoC) with implemented Cortex-A72 cores include: a .:

  • Broadcom BCM2711 ( Raspberry Pi 4 Model B; the main memory is on its own chip instead of on the SoC)
  • HiSilicon Kirin 950, 955
  • NXP i.MX8QM
  • Mediatek MT6797 (T), MT8173 (C), MT8176
  • Qualcomm Snapdragon 650, 652, 653
  • Rockchip RK3399
  • Samsung Exynos 7650

ARM Cortex-A73

The ARM Cortex-A73 MPCore introduced in 2016 is a 64-bit multicore processor with up to four Cortex-A73 cores, each of which implements the ARMv8 instruction set. The core design is based on that of the Cortex-A17 and does not belong to the A15 / A57 / A72 development series. It is a 2-way superscalar out-of-order design with an 11-stage pipeline, the L1 cache has 64 kB for instructions and 32 kB or 64 kB for data. All cores in the cluster can access the shared L2 cache (256 kB to 8 MB) at the same time. ARM specifies the clock with 2.8 GHz, a cluster with four cores, 64 kB / 64 kB L1 and 2 MB L2 cache should be about 5 mm² implemented in TSMCs 10FF.

properties

crisps

  • HiSilicon Kirin 710, 970
  • Mediatek MT6799
  • Amlogic S905

ARM Cortex-A55

The ARM Cortex-A55 MPCore, the successor to the Cortex-A53, presented in 2017 is a 64-bit multicore processor with up to 8 Cortex-A55 cores, which are arranged in a DynamIQ cluster and implements an ARMv8.2 architecture . It is a dual-decode / dual-issue- in-order design, the integer pipeline length is 8 stages as with the Cortex-A53, the NEON / FP pipeline 10 stages (NEON / FP is still optional ). Instead of a load / store unit, the Cortex-A55 now has a separate load and store unit. Each core has a 16 KiB to 64 KiB L1 cache for commands and data as well as an optional private L2 cache (64 KiB, 128 KiB or 256 KiB). An optional shared L3 cache (1 MiB, 2 MiB or 4 MiB) can be accessed via the DynamIQ Shared Unit.

properties

  • Up to 8 A55 cores per DynamIQ cluster, 4-7 A55 cores in combination with Cortex-A75 or -A76 (each max. 4)
  • NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware virtualization support
  • Thumb-2 instruction set
  • TrustZone security extensions

crisps

  • HiSilicon Kirin 810, 820, 980, 985, 990

ARM Cortex-A75

The ARM Cortex-A75 MPCore, the successor to the Cortex-A73, presented in 2017, is a 64-bit multicore processor with up to 8 Cortex-A75 cores, which are arranged in a DynamIQ cluster and implements an ARMv8.2 architecture . It is a 3-Decode / 6-Issue- Out-of-Order -Design, the integer- pipeline -length is like with the Cortex-A73 11 steps; all units now have their own, enlarged queues . A store unit was added for NEON / FP, the pipeline length is now 13 steps instead of 12. Each core has a 64 KiB L1 cache for commands and data as well as a private 256 KiB or 512 KiB L2 cache. An optional shared L3 cache (1 MiB, 2 MiB or 4 MiB) can be accessed via the DynamIQ Shared Unit.

properties

  • Up to 8 cores per DynamIQ cluster (but only max. 4 Cortex-A75) in combination with Cortex-A55
  • NEON SIMD extensions
  • VFPv4 floating point unit
  • Hardware virtualization support
  • Thumb-2 instruction set
  • TrustZone security extensions

ARM Cortex-A76

In May 2018, the ARM Cortex-A76 was presented as the successor to the A75. Like its predecessor, the micro-architecture is based on the ARMv8.2 instruction set, the processor blueprints / IP are available for 10 nm and 7 nm lithography processes; the maximum clock rate is specified as 3.0 GHz (7 nm).

The first SoC with A76 is the Kirin 980 from HiSilicon in 7 nm production technology: two A76 cores each work here with different clock frequencies together with four A55 cores in a 2 + 2 + 4 DynamIQ cluster. The first smartphone with a Kirin 980 is the Huawei Mate 20 at the end of 2018.

For safety-critical automotive applications, ARM introduced the Cortex-A76AE version in September 2018.

properties

  • Cache organization as before: L1 : data 8-64 KiB, instructions 8-64 iKB, L2 : 256/512 KiB per core, L3 via the DynamIQ shared unit: up to 4 MiB per cluster.
  • up to 8 cores per DynamIQ cluster (but only max. 4 Cortex-A76) in combination with Cortex-A55.
  • Up to 4 (A75: 3) instructions / cycle can be decoded and 8 (A75: 6) dispatched, the IPC values ​​can be up to 30% higher than with the predecessor A75. The number of integer units has been increased to 3 (A75: 2).
  • Both NEON SIMD units are now designed with a width of 128 bits.
  • Compared to the A75 in 10 nm, ARM states either 40% more computing power or 50% less energy consumption, but a large part of this effect is likely due to the smaller structure size of 7 nm.
  • An unspecified "higher AI / ML " performance is specified.

crisps

  • HiSilicon Kirin 810, 820, 980, 985, 990

ARM Cortex-A65AE

The ARM Cortex-A65AE was presented in December 2018. The micro-architecture is based on the ARMv8.2 instruction set, it is the first ARM core to support SMT and, like the Cortex-A76AE, it is intended for automotive applications. Up to 8 cores can be accommodated in a DynamIQ cluster.

ARM Cortex-A77

In May 2019, the ARM Cortex-A77 was presented as the successor to the A76. Like its predecessor, the micro-architecture is based on the ARMv8.2 instruction set, the processor blueprints / IP are available for 7 nm lithography processes, the maximum clock rate is specified as 3.0 GHz.

properties

  • Cache organization: L1 : data 64 KiB, instructions 64 KiB, L2 : 256/512 KiB per core, L3 optionally via the DynamIQ shared unit: 512 KiB to 4 MiB per cluster.
  • Up to 8 cores per DynamIQ cluster (but only max. 4 Cortex-A77) in combination with Cortex-A55.
  • Up to 6 (A76: 4) instructions / cycle can be decoded and 10 (A76: 8) can be dispatched, the number of integer units was set to 4 (A76: 3), the number of branch units to 2 (A76: 1 ) elevated.
  • For the first time, ARM introduced a macro-ops cache with 1500 entries.
  • ARM indicates 20% more computing power compared to the A76.

Licensees and Products (ARMv7-A)

All-winner AMLogic Apple Broadcom Freescale HiSilicon MediaTek Nvidia Rockchip Samsung ST-Ericsson TI
Cortex-A8 A10,
A13 		A4 i.MX5x RK2918 Exynos 3 OMAP 3
AM335x
Cortex-A9 AML7366-M and
AML8726-
(M, M3L, M6, MX) 		A5 BCM11311 various
models from
the i.MX6 series 		K3V2 MT6575, MT6577,
MT8317T, MT8377 		Tegra 2 ,
Tegra 3 ,
Tegra 4i 		RK3066 ,
RK3188 ,
RK3168 		Exynos 4 Nova U8500 OMAP 4
Cortex-A7 A20 ,
A31 		BCM2836 i.MX6ULL,
i.MX6UltraLite,
i.MX7Dual family 		MT5807, MT6517, MT6572,
MT6582 (M), MT6589 (T),
MT6592, MT8121,
MT8125, MT8127,
MT8312, MT8389 		STM32MP1
Cortex-A12 RK32XX
Cortex-A15 Tegra 4 ,
Tegra K1 		Exynos 5
Dual, Quad 		Nova A9600 OMAP 5
Cortex-A17 MT5861, MT5890
big.LITTLE
A7 + A12
big.LITTLE
A7 + A15 		K3V3 MT8135 Exynos 5
Octa
big.LITTLE
A7 + A17 		MT5595, MT6595 (M / T)

See also

Web links

Individual evidence

  1. ^ ARM: Press release of October 4, 2005.
  2. ↑ a b c Frank Riemenschneider: Cortex-A5 for microcontroller and multiprocessing applications. In: Elektroniknet.de , June 4, 2010. ( Memento from September 23, 2015 in the Internet Archive )
  3. ↑ a b ARM: ARM Unveils Cortex-A9 Processors For Scalable Performance and Low-Power Designs , press release of October 3, 2007.
  4. ↑ ARM: Processor variants ( Memento from August 21, 2017 in the Internet Archive ) In: ARM Cortex-A9 Technical Reference Manual r4p1 , 2016.
  5. ↑ Cortex-A9 Processor at ARM.com, accessed August 20, 2013.
  6. ↑ ARM: Offspring for the Cortex-A family In: heise online , October 22, 2009.
  7. ↑ ARM: ARM Unveils Cortex-A15 MPCore Processor to Dramatically Accelerate Capabilities of Mobile, Consumer and Infrastructure Applications , press release of September 8, 2010.
  8. ↑ Frank Riemenschneider: Cortex-A15 is aimed at the communication and server market. In: Elektroniknet.de , March 10, 2011. ( Memento from September 23, 2015 in the Internet Archive )
  9. ↑ a b c d e f Frank Riemenschneider: ARM pairs Cortex-A7 and Cortex-A15. In: Elektroniknet.de , June 13, 2012. ( Memento from September 23, 2015 in the Internet Archive )
  10. ↑ ARM introduces the new Cortex-A7 SoC processor core In: heise online , October 20, 2011.
  11. ↑ ARM: Cortex-A7 MPCore Revision: r0p3 - Technical Reference Manual , pp. 6–2, 7-2.
  12. ↑ The MediaTek MT6592 chipset benchmark test leaked online In: GIZMOCHINA , October 17, 2013.
  13. ↑ MediaTek Helio P25 Specifications In: mediatek.com .
  14. ↑ a b Frank Riemenschneider: ARM reveals new 64-bit cores. In: Elektroniknet.de , October 30, 2012. ( Memento from March 4, 2016 in the Internet Archive )
  15. ↑ Frank Riemenschneider: ARM Cortex-A12: The successor to the Cortex-A9 is ready. In: Elektroniknet.de , August 13, 2013. ( Memento from September 23, 2015 in the Internet Archive )
  16. ↑ a b Benjamin Benz: New ARM core for mid-range smartphones In: heise online , February 11, 2014.
  17. ^ ARM: Cortex-A17 and an enhanced suite of IP targeted at the mid-range mobile market. , February 13, 2014.
  18. ↑ ARM: ARM Cortex-A17 / Cortex-A12 processor update. , September 30, 2014.
  19. ^ ARM: Cortex-A72 Processor.
  20. ↑ Frank Riemenschneider: ARM Cortex-A72 should set a new benchmark for energy efficiency. In: CRN , February 17, 2015.
  21. ↑ Frank Riemenschneider : ARM chief architect presents Cortex-A72 details. ( Memento from May 1, 2015 in the web archive archive.today ), Article at Elektroniknet.de from April 29, 2015.
  22. ↑ Security - the Fundamental Element in Next-Gen Networks. Retrieved December 17, 2019 .
  23. ↑ Andrei Frumusanu : The ARM Cortex A73 - Artemis Unveiled. Article on AnandTech.com from May 29, 2016.
  24. ↑ https://www.anandtech.com/show/13614/arm-delivers-on-cortex-a76-promises
  25. ↑ https://developer.arm.com/products/processors/cortex-a/cortex-a76
  26. ↑ https://developer.arm.com/ip-products/processors/cortex-a/cortex-a76ae
  27. ↑ https://www.anandtech.com/show/13727/arm-announces-cortex65ae-for-automotive-first-smt-cpu-core
  28. ↑ https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae
  29. ↑ https://www.anandtech.com/show/14384/arm-announces-cortexa77-cpu-ip
  30. ↑ https://developer.arm.com/ip-products/processors/cortex-a/cortex-a77
List of ARM processors
ARM1 family

ARMv1 (ARM1)

ARM2 family

ARMv2 (ARM2) | ARMv2a (ARM250)

ARM3 family

ARMv2a (ARM2a)

ARM6 family

ARMv3 (ARM60, ARM600, ARM610)

ARM7 family

ARMv3 (ARM700, ARM710, ARM710a, ARM7100, ARM7500, ARM7500FE)

ARM7TDMI family

ARMv4T (ARM7TDMI, ARM7TDMI-S, ARM710T, ARM720T, ARM740T) | ARMv5TEJ (ARM7EJ-S)

StrongARM family

ARMv4 (SA-110, SA-1110)

ARM8 family

ARMv4 (ARM810)

ARM9TDMI family

ARMv4T (ARM9TDMI, ARM920T, ARM922T, ARM940T)

ARM9E family

ARMv5TE (ARM946E-S, ARM966E-S, ARM968E-S, ARM996HS) | ARMv5TEJ (ARM926EJ-S)

ARM10E family

ARMv5TE (ARM1020E, ARM1022E) | ARMv5TEJ (ARM1026EJ-S)

ARM11 family

ARMv6 (ARM1136J-S, ARM1136JF-S) | ARMv6T2 (ARM1156T2-S, ARM1156T2F-S) | ARMv6KZ (ARM1176JZ-S, ARM1176JZF-S) | ARMv6K (ARM11 MPCore)

Cortex-A family

ARMv7-A (Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A12, Cortex-A15, Cortex-A17) | ARMv8-A (Cortex-A35, Cortex-A53, Cortex-A57, Cortex-A72, Cortex-A73)

Cortex-M family

ARMv6-M (Cortex-M0, Cortex-M1) | ARMv7-M ( Cortex-M3 , Cortex-M4 ) | ARMv8-M (Cortex-M23, Cortex-M33, Cortex-M35P) | ARMv8.1-M (Cortex-M55)

Cortex-R family

ARMv7-R (Cortex-R4, Cortex-R4F)