Intel iAPX 432

The Intel iAPX 432 was Intel's first 32-bit microprocessor . It was introduced in 1981 as a set of three integrated circuits and was planned as the basic Intel design for the 1980s. Advanced functions such as preemptive multitasking and memory management were implemented in the hardware, which is why the design was also called the “micro-mainframe”.

The processor's data structure support made it possible to implement modern operating systems with much less program code than conventional CPUs - the 432 instead did most of the work in-house in the hardware. Compared to other processors, the chip structure was extremely complex. Intel's engineers did not manage to use the semiconductor technology of the time to convert the concept into an efficient implementation. The CPU was very slow and expensive, and Intel's plans to replace the x86 architecture with the iAPX 432 ended in economic disaster.

The abbreviation iAPX stood for i ntel A dvanced P rocessor ar chi tecture , where the X came from the Greek letter Chi ; if you "APX" itself as Greek writing indicated ( Alpha , Rho Chi), it is even impossible tecture.

history

development

The 432 project began in 1975 as the i8800 and should join the existing 8008 and 8080 product lines . The design was planned as a pure 32-bit design from the start. It was supposed to be much more powerful and complex than the previous Intel processors and was far beyond the capabilities of the process technology of the time. The CPU therefore had to be divided into several chips.

The general data processor (GDP) consisted of two chips. One chip (the 43201) fetched and decoded the commands, the second (43202) carried them out. An I / O controller was optionally available with the 43203 interface processor (IP). The three-chip combination consisted of 250,000 transistors, making it one of the most extensive designs of its time. For example, the Motorola 68000 consisted of around 68,000 transistors, a third of which were for the microcode .

In 1983, Intel introduced two additional chips for the iAPX 432 Interconnect Architecture , the 43204 Bus Interface Unit (BIU) and the 43205 Memory Control Unit (MCU). With them, multiprocessor systems with up to 63 nodes became possible.

The project's mistakes

Several design features made the iAPX 432 much slower than it could have been. The two-chip implementation of the GDP limited it to the speed of the wiring on the mainboard. However, this was less of a problem. Far more serious was the lack of caches and registers . Also, the command set slowed performance because instead of the usual, lying on word boundaries ( word-aligned ) instructions fixed length when lying on bit boundaries ( bit-aligned ) instructions of variable length were used. The decoding of the instructions became complex and slow. The BIU was supposed to support fault-tolerant systems, which resulted in a noticeable overhead on the bus. The bus spent 40 percent of the time waiting cycles.

Investigations after the end of the project showed that the biggest problem was probably with the compiler , which in all cases used general and slow commands instead of using simple and fast commands at least where it would have been useful. For example , the iAPX 432 had a very expensive intermodular procedure call instruction that the compiler used for all calls. He ignored the much faster jump commands. Another very slow call was enter_environment , which was used to set up memory protection. The compiler called it for every single variable in the system, although most of them ran in an existing environment and did not need to be checked. To make the situation even worse, call-by-value rather than call-by-reference was used, which in many cases required huge memory copies.

aftermath

The lesson learned from the iAPX 432 failure is that supporting objects at the CPU level leads to a complex design that inevitably runs slowly. Since the iAPX 432 appeared, nobody has created a similar design. In fact, it looks like supporting object orientation wasn't the problem at all. The iAPX 432 suffered from problems that would have made any chip design slow.

Intel had invested vast amounts of time and money in developing and marketing the 432, had a capable team on it, and was reluctant to simply abandon the team after that failure. Under the leadership of the new chief designer Glenford Myers, the main processor was to be redeveloped and then built as part of a joint venture with Siemens . The i960 CPU series later emerged from this project and enjoyed great popularity in the embedded market for a long time. In 1990, the responsible team gave up the i960 and began developing the P6 core, which has been successful to this day and which debuted in the Pentium Pro in 1995 and was later sold as the Pentium M in a further developed form . The Core 2 microarchitecture, to which Intel came back after problems with the NetBurst architecture , is also based on the P6 core.

literature

• Josef Koller: 16 Bit Microcomputer , 1st edition, Hofacker Verlag, Munich 1981, ISBN 3-921682-80-0 , pp. 371-372.

Web links

• Including the dies of the General Data Processor