Reduced instruction set computer

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"RISC" redirects here. For other uses, see RISC (disambiguation).

The acronym RISC (pronounced risk), for reduced instruction set computer represents a CPU design strategy emphasizing the insight that simplified instructions which "do less" may still provide for higher performance if this simplicity can be utilized to make instructions execute very fast. Many proposals for a "precise" definition has been attempted, however, the term is being slowly replaced by the more descriptive load-store architecture (see below). Well known RISC families include DEC Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture (including PowerPC), and SPARC.

Being an old idea, some aspects attributed to the first RISC-labeled designs (around 1975) include the discovery that compilers of the time were often unable to take advantage of features intended to facilitate coding, and that complex addressing took many cycles to perform. It was argued that such functions would better be performed by sequences of simpler instructions if this could yield implementations simple enough to cope with really high frequencies, and small enough to leave room for many registers[1], factoring out slow memory accesses. Uniform, fixed length instructions with arithmetics restricted to registers were chosen to ease pipelining in these simple designs, with special load-store instructions accessing memory.

non-RISC design philosophy

Further information: CPU design

In the early days of the computer industry, programming was done in assembly language or machine code, which encouraged powerful and easy to use instructions. CPU designers therefore tried to make instructions that would do as much work as possible. With the advent of higher level languages, computer architects also started to create dedicated instructions to directly implement certain central mechanisms of such languages. Another general goal was to provide every possible addressing mode for every instruction, known as orthogonality, to ease compiler implementation. Arithmetic operations could therefore often have results as well as operands directly in memory (in addition to register or immediate).

The attitude at the time was that hardware design was easier than compiler design, so large parts of the complexity went into the hardware (and/or microcode). After the RISC philosophy came onto the scene, this design philosophy became retroactively termed Complex Instruction Set Computer (CISC).

CPUs also had relatively few registers, for several reasons:

  • CPU registers are more expensive than external memory locations; large register sets were cumbersome with limited circuit boards or chip integration.
  • A large number of registers requires a large number of instruction bits as register specifiers, meaning less dense code (see below).
  • More registers also implies more time consuming saving and restoring of register contents on the stack.

Another force that encouraged complexity was very limited memories (in the order of kilobytes). It was therefore advantageous for the density of information held in computer programs to be very high, leading to features such as highly encoded, variable length instructions, doing both calculation and data loading (as mentioned above). At that time, these issues were of higher priority than the ease of decoding such instructions. Another reason was that memory was also quite slow, usually implemented using ferrite core memory technology; by having dense information packing, one could decrease the frequency with which one had to access this slow resource.

While on a very different scale, the above situation is actually not unlike the one we have seen for the last 10-15 years. Modern computers faces similar limiting factors: Main memories are slow compared to the CPU and the fast cache memories employed to overcome this are instead limited in size. This would in part explain why highly encoded instruction sets has proven to be well as useful as RISC designs in modern computers.

RISC design philosophy

In the mid 1970s researchers at IBM (and similar projects elsewhere) demonstrated that the majority of combinations of these orthogonal addressing modes and instructions were not used by most programs generated by compilers available at the time. It proved difficult in many cases to write a compiler with more than limited ability to take advantage of the features provided by conventional CPUs.

It was also discovered that, on microcoded implementations of certain architectures, complex operations tended to be slower than a sequence of simpler operations doing the same thing. This was in part an effect of the fact that many designs were rushed, with little time to optimize or tune every instruction, but only those used most often. One infamous example was the VAX's INDEX instruction, which ran slower than a loop implementing the same code.[2]

As mentioned elsewhere, core memory had since long been slower than many CPU designs. The advent of semiconductor memory reduced this difference, but it was still apparent that more registers (and later caches) would allow higher CPU operating frequencies. Additional registers would require sizeable chip or board areas which, at the time (1975), could be made available if the complexity of the CPU logic was reduced.

Yet another impetus of both RISC and other designs came from practical measurements on real-world programs. Andrew Tanenbaum summed up many of these, demonstrating that processors often had oversized immediates. For instance, he showed that 98% of all the constants in a program would fit in 13 bits, yet many CPU designs dedicated 16 or 32 bits to store them. This suggests that, to reduce the number of memory accesses, a fixed length machine could store constants in unused bits of the instruction word itself, so that they would be immediately ready when the CPU needs them (much like immediate addressing in a conventional design). This required small opcodes in order to leave room for a reasonably sized constant in a 32-bit instruction word.

Since many real-world programs spent most of their time executing simple operations, some researchers decided to focus on making those operations as fast as possible. The clock rate of a CPU is limited by the time it takes to execute the slowest sub-operation of any instruction, thus speeding up that cycle-time (perhaps by simplifying decoding, or addressing modes) often also speeds the execution of other instructions. [1]. The focus on "reduced instructions" led to the resulting machine being called a "reduced instruction set computer" (RISC). The goal was to make instructions so simple that they could easily be pipelined, in order to achieve

  1. a single clock throughput
  2. at high frequences.

Later, it was noticed that the single property that sets virtually every RISC CPU apart from other designs were that the CPU either perform

  1. an operation on registers (and/or immediates) or
  2. a load of register data to or from memory.

This has become known as a load-store architecture, and is today the prefered term in many circles.

Other solutions

Below are some strategies on how to increase performance that have been implemented in RISC as well as non-RISC designs over the years:

Parallel computing

In the early 1980s it was thought that existing design was reaching theoretical limits. Future improvements in speed would be primarily through improved semiconductor "process", that is, smaller features (transistors and wires) on the chip. The complexity of the chip would remain largely the same, but the smaller size would allow it to run at higher clock rates. A considerable amount of effort was put into designing chips for parallel computing, with built-in communications links. Instead of making faster chips, a large number of chips would be used, dividing up problems among them. However, history has shown that the original fears were not valid and there were a number of ideas that dramatically improved performance as far back as the mid-1960s.

Pipelining

One idea was to include a pipeline which would break down instructions into steps, and work on one step of several different instructions at the same time. A normal processor might read an instruction, decode it, fetch the memory the instruction asked for, perform the operation, and then write the results back out. The key to pipelining is the observation that the processor can start reading the next instruction as soon as it finishes reading the last, meaning that there are now two instructions being worked on (one is being read, the next is being decoded), and after another cycle there will be three. While no single instruction is completed any faster, the next instruction would complete right after the previous one. The result was a much more efficient utilization of processor resources, epitomized in the 1960s by the early supercomputer, the CDC 6600.

Superscalar

Another solution was to use several processing elements inside the processor and run them in parallel. Instead of working on one instruction to add two numbers, these superscalar processors would look at the next instruction in the pipeline and attempt to run it at the same time in an identical unit. However, this can be difficult to do, as many instructions in computing depend on the results of some other instruction.

Typical characteristics of RISC

For any given level of general performance, a RISC chip will typically have many fewer transistors dedicated to the core logic which originally allowed designers to increase the size of the register set and increase internal parallelism.

Other features, which are typically found in RISC architectures are:

  • Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding.
  • Identical registers, allowing any register to be used in any context, simplifying compiler design (although normally separate floating point registers)
  • Simple addressing modes, with complex addressing performed via sequences of arithmetic and/or load-store operations
  • Few data types in hardware, some CISCs has byte strings instructions, or supports complex numbers; this is so far unlikely to be found on a RISC.

Exceptions abound, of course, within both CISC and RISC.

RISC designs are also more likely to feature a Harvard memory model, where the instruction stream and the data stream are conceptually separated; this means that modifying the memory where code is held might not have any effect on the instructions executed by the processor (because the CPU has a separate instruction and data cache), at least until a special synchronization instruction is issued. On the upside, this allows both caches to be accessed simultaneously, which can often improve performance.

Many of these early designs also shared the characteristic of having a branch delay slot. A branch delay slot is an instruction space immediately following a jump or branch. The instruction in this space is partially executed whether or not the branch is taken (in other words the effect of the branch is delayed). This instruction keeps the ALU of the CPU busy for the extra time normally needed to perform a branch. Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as PowerPC, more recent versions of SPARC, and MIPS).

Early RISC

The first system that would today be known as RISC was not at the time; it was the CDC 6600 supercomputer, designed in 1964 by Jim Thornton and Seymour Cray. Thornton and Cray designed it as a number-crunching CPU (with 74 opcodes, compared with a 8086's 400) plus 12 simple computers called "peripheral processors" to handle I/O and most other operating system functions. The CDC 6600 had a load-store architecture with only two addressing modes (register+register, and register+immediate constant). There were eleven pipelined functional units for arithmetic and logic, plus five load units and two store units (the memory had multiple banks so all load-store units could operate at the same time). The basic clock cycle/instruction issue rate was 10 times faster than the memory access time.

Another early load-store machine was the Data General Nova minicomputer, designed in 1968.

The earliest attempt to make a chip-based RISC CPU was a project at IBM which started in 1975. Named after the building where the project ran, the work led to the IBM 801 CPU family which was used widely inside IBM hardware. The 801 was eventually produced in a single-chip form as the ROMP in 1981, which stood for Research (Office Products Division) Mini Processor. As the name implies, this CPU was designed for "mini" tasks, and when IBM released the IBM RT-PC based on the design in 1986, the performance was not acceptable. Nevertheless the 801 inspired several research projects, including new ones at IBM that would eventually lead to their POWER system.

The most public RISC designs, however, were the results of university research programs run with funding from the DARPA VLSI Program. The VLSI Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics.

UC Berkeley's RISC project started in 1980 under the direction of David Patterson, based on gaining performance through the use of pipelining and an aggressive use of registers known as register windows. In a normal CPU one has a small number of registers, and a program can use any register at any time. In a CPU with register windows, there are a huge number of registers, e.g. 128, but programs can only use a small number of them, e.g. 8, at any one time. A program that limits itself to 8 registers per procedure can make very fast procedure calls: The call simply moves the window "down" by 8, to the set of 8 registers used by that procedure, and the return moves the window back. (On a normal CPU, most calls must save at least a few registers' values to the stack in order to use those registers as working space, and restore their values on return.)

The RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer CISC designs of the era) RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. They followed this up with the 40,760 transistor, 39 instruction RISC-II in 1983, which ran over three times as fast as RISC-I.

At about the same time, John L. Hennessy started a similar project called MIPS at Stanford University in 1981. MIPS focused almost entirely on the pipeline, making sure it could be run as "full" as possible. Although pipelining was already in use in other designs, several features of the MIPS chip made its pipeline far faster. The most important, and perhaps annoying, of these features was the demand that all instructions be able to complete in one cycle. This demand allowed the pipeline to be run at much higher speeds (there was no need for induced delays) and is responsible for much of the processor's speed. However, it also had the negative side effect of eliminating many potentially useful instructions, like a multiply or a divide.

In the early years, the RISC efforts were well known, but largely confined to the university labs that had created them. The Berkeley effort became so well known that it eventually became the name for the entire concept. Many in the computer industry criticized that the performance benefits were unlikely to translate into real-world settings due to the decreased memory efficiency of multiple instructions, and that that was the reason no one was using them. But starting in 1986, all of the RISC research projects started delivering products. In fact, almost all modern RISC processors are direct copies of the RISC-II design.

Later RISC

Berkeley's research was not directly commercialized, but the RISC-II design was used by Sun Microsystems to develop the SPARC, by Pyramid Technology to develop their line of mid-range multi-processor machines, and by almost every other company a few years later. It was Sun's use of a RISC chip in their new machines that demonstrated that RISC's benefits were real, and their machines quickly outpaced the competition and essentially took over the entire workstation market.

John Hennessy left Stanford (temporarily) to commercialize the MIPS design, starting the company known as MIPS Computer Systems. Their first design was a second-generation MIPS chip known as the R2000. MIPS designs went on to become one of the most used RISC chips when they were included in the PlayStation and Nintendo 64 game consoles. Today they are one of the most common embedded processors in use for high-end applications.

IBM learned from the RT-PC failure and went on to design the RS/6000 based on their new POWER architecture. They then moved their existing AS/400 systems to POWER chips, and found much to their surprise that even the very complex instruction set ran considerably faster. POWER would also find itself moving "down" in scale to produce the PowerPC design, which eliminated many of the "IBM only" instructions and created a single-chip implementation. Today the PowerPC is one of the most commonly used CPUs for automotive applications (some cars have over 10 of them inside). It was also the CPU used in most Apple Macintosh machines sold until 2006. Starting in February 2006, Apple switched their PowerPC products to Intel x86 processors.

Almost all other vendors quickly joined. From the UK similar research efforts resulted in the INMOS transputer, the Acorn Archimedes and the Advanced RISC Machine line, which is a huge success today. Companies with existing CISC designs also quickly joined the revolution. Intel released the i860 and i960 by the late 1980s, although they were not very successful. Motorola built a new design called the 88000 in homage to their famed CISC 68000, but it saw almost no use and they eventually abandoned it and joined IBM to produce the PowerPC. AMD released their 29000 which would go on to become the most popular RISC design of the early 1990s.

Today the vast majority of all 32-bit CPUs in use are RISC CPUs, and microcontrollers. RISC design techniques offers power in even small sizes, and thus has become dominant for low-power 32-bit CPUs. Embedded systems are by far the largest market for processors: while a family may own one or two PCs, their car(s), cell phones, and other devices may contain a total of dozens of embedded processors. RISC had also completely taken over the market for larger workstations for much of the 90s (until taken back by cheap PC-based solutions). After the release of the Sun SPARCstation the other vendors rushed to compete with RISC based solutions of their own. The high-end server market today is almost completely RISC based.

RISC and x86

However, despite many successes, RISC has made few inroads into the desktop PC and commodity server markets, where Intel's x86 platform remains the dominant processor architecture (Intel is facing increased competition from AMD, but even AMD's processors implement the x86 platform, or a 64-bit superset known as x86-64). There are three main reasons for this. One, the very large base of proprietary PC applications are written for x86, whereas no RISC platform has a similar installed base, and this meant PC users were locked into the x86. The second is that, although RISC was indeed able to scale up in performance quite quickly and cheaply, Intel took advantage of its large market by spending vast amounts of money on processor development. Intel could spend many times as much as any RISC manufacturer on improving low level design and manufacturing. The same could not be said about smaller firms like Cyrix and NexGen, but they realized that they could apply pipelined design philosophies and practices to the x86-architecture — either directly as in the 6x86 and MII series, or indirectly (via extra decoding stages) as in Nx586 and AMD K5. Later, more powerful processors such as Intel P6 and AMD K6 had similar RISC-like units that executed a stream of micro-operations generated from decoding stages that split most x86 instructions into several pieces. Today, these principles have been further refined and are used by modern x86 processors such as Intel Core 2 and AMD K8. The first available chip deploying such techniques was the NexGen Nx586, released in 1994 (while the AMD K5 was severely delayed and released in 1995).

As of 2007, the x86 designs (whether Intel's or AMD's) are as fast as (if not faster than) the fastest true RISC single-chip solutions available.[3]

Cost

Consumers are interested in speed, energy efficiency, cost per chip, and compatibility with existing software rather than the cost of development of new chips.[citation needed] This has led to an interesting chain of events. As the complexity of developing ever more advanced CPUs rises, the cost of both development and fabrication of high-end CPUs has exploded. The cost gains given by RISC are now dwarfed by the high costs of developing any modern CPU. Today, only the biggest chip makers are able to make high performing CPUs. The result is that virtually all RISC platforms with the exception of IBM's Power Architecture have greatly shrunk in scale of development of high performing CPUs (like SPARC and MIPS) or were abandoned (like Alpha and PA-RISC) during the 00s. As of 2007, a RISC chip is (again) the fastest CPU in SPECint and SPECfp, which is IBM's Power6 CPU. [citation needed]

Still, RISC designs have led to a number of successful platforms and architectures, some of the larger ones being:

Alternative terminology

Over many years, RISC instruction sets tended to grow in size, and in fact, some processors such as the INMOS Transputer had instruction sets as large as, say, the IBM System/370. Thus, industry observers started using the term "register-register" or "load-store" to describe RISC processors, since this is the key element of all such designs. Instead of the CPU itself handling many addressing modes, a load-store architecture employs a separate unit dedicated to handling very simple forms of load and store operations.

See also

Notes and references

  1. ^ in place of complex logic or microcode (transistors were then a scarce resource)
  2. ^ Patterson, D. A. and Ditzel, D. R. 1980. The case for the reduced instruction set computer. SIGARCH Comput. Archit. News 8, 6 (Oct. 1980), 25-33. DOI= http://doi.acm.org/10.1145/641914.641917
  3. ^ http://www.spec.org/cpu2006/results/

External links

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