AMD Turion 64 X2
| << AMD Turion 64 X2 >> | |
|---|---|
 Turion 64 X2 emblem |
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| Production: | 2006 to 2008 |
| Producer: | AMD |
| Processor clock: | 1.6 GHz to 2.4 GHz |
| HT cycle: | 800 MHz |
| L2 cache size: | 512 KiB to 1 MiB |
| Instruction set : | x86 / AMD64 |
| Microarchitecture : | K9 / AMD64 |
| Base: | Base S1 |
Names of the processor cores:
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Turion 64 X2 is the new microprocessor family with two processor cores officially presented by AMD on May 17, 2006 . Like its single-core counterpart, the Turion 64 , it is especially optimized for energy-saving operation in notebooks .
technology
In contrast to its predecessor, the Turion 64 X2 is a derivative of the Athlon 64 X2 CPU and therefore also has two cores ( dual core ). Because of this relationship, it also has a dual-channel memory controller with support for DDR-2/667 memory. Because of these changes, base S1 is now used instead of base 754 . The HyperTransport link is also clocked at 800 MHz. The first CPUs were manufactured in 90 nm, newer ones are based on 65 nm technology.
Designation scheme
The designation scheme used has been retained and, as before, is primarily based on maximum power consumption and computing power. In order to distinguish the Turion 64 X2 from the Turion 64, the new abbreviation T L was introduced. The Turion 64 is again available with different L2 cache sizes. The T L stands for the power loss. The higher the letter in the alphabet, the lower it is. Common names are TK and TL, whereby TL is more suitable for mobile use.
marketing
AMD positions the marketing concept officially known as Turion 64 X2 Mobile Technology against that of the Centrino Duo from Intel . In contrast to Intel, however, AMD does not bind the use of the brand name to the use of certain, primarily in-house chipsets , but leaves the choice of components to the manufacturers.
future
As successors to the Turion 64 X2 processors, AMD has presented the new processors under the name Turion X2 and Turion X2 Ultra , which come on the new AMD notebook platform "Puma" . The new processors were developed under the code name "Griffin" and represent a hybrid between the K9 and K10 generation.
Model data base S1
All processors for socket S1 have a memory controller with two channels (128 bit, dual-channel operation) for DDR2-SDRAM .
Taylor
- Revision F2
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 256 KiB per core with processor clock
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , AMD64 , PowerNow! , NX-Bit , AMD-V
- Socket S1 , HyperTransport with 800 MHz (HT1600)
- Operating voltage (VCore): 0.8-1.1V
- Power consumption ( TDP ): 31 W
- Release DATE: May 17, 2006
- Manufacturing technology: 90 nm ( SOI )
- The size: 183 mm² with 153.8 million transistors
- Clock frequency: 1,600 MHz
- TL-50: 1,600 MHz
Trinidad
- Revision F2
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , AMD64 , PowerNow! , NX-Bit , AMD-V
- Socket S1 , HyperTransport with 800 MHz (HT1600)
- Operating voltage (VCore): 0.8-1.1V
- Power consumption ( TDP ): 31–35 W
- Release DATE: May 17, 2006
- Manufacturing technology: 90 nm ( SOI )
- The size: 183 mm² with 153.8 million transistors
- Clock frequencies: 1,600–2,200 MHz
- TL-52: 1,600 MHz (31 W TDP)
- TL-56: 1,800 MHz (33 W TDP)
- TL-60: 2,000 MHz (35 W TDP)
- TL-64: 2,200 MHz (35 W TDP)
Tyler
- Revision G1 / G2
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , AMD64 , PowerNow! , NX-Bit , AMD-V
- Socket S1 , HyperTransport with 800 MHz (HT1600)
- Operating voltage (VCore): 0.8-1.1V
- Power consumption ( TDP ): 31–35 W
- Release DATE: May 4, 2007
- Manufacturing technology: 65 nm ( SOI )
- Clock frequencies: 1,700–2,400 MHz
- 31 W TDP:
- TL-53: 1,700 MHz
- TL-56: 1,800 MHz
- TL-58: 1,900 MHz
- TL-60: 2,000 MHz
- 35 W TDP:
- TL-62: 2,100 MHz
- TL-64: 2,200 MHz
- TL-66: 2,300 MHz
- TL-68: 2,400 MHz
- 31 W TDP:
